I am currently using the sige 5Hp lib.
I found if you use BB layer to enclose
more than one bipolar transistors inside
it,you can pack those transistors much
closer.And the chip designed in this way works.
Yesterday I found if you use BP layer to enclose
more than one CMOS inside the deep trench, you can
pack CMOSes much closer.
It doesn't violate the rule since Cadence tool
says it's all right.But since nobody did that in
my group,I am not sure whether it is right.
Can anybody give me some suggestions?
What's the function of these two layers?Why
CMOSes and bipolars can be packed much closer
if I use these layers.