by First Call for Papers
ASP-DAC'95 CHDL'95 VLSI'95
Asia and South Pacific IFIP Conference on IFIP Conference on
Design Automation Hardware Description Very Large Scale
Conference Languages and their Integration
Applications
with EDA Technofair'95
Aug.29-Sept.1, 1995
Nippon Convention Center, Makuhari, Chiba, JAPAN
Sponsored by:
IEICE (Institute of Electronics,
Information and Communication Engineers)
IPSJ (Information Pro cessing So ciety of Japan)
IFIP WG10.2,IFIP WG10.5
IEEE Circuits and Systems Society
IEEE Computer Society (Under negotiation)
Supported by:
EIAJ (Electronics Industries Association, Japan)
In cooperation with:
JIPC (The Japan Institute of Printed Circuit)
Aims of the Conference:
The goal of the joint meeting of 1995 ASP-DAC/CHDL/VLSI is to
provide a forum for presentation, discussion, and observation of the
state-of-the-art of a wide range of CAD/DA/VLSI sciences and
technologies. The format of the meeting is intended to cultivate and
promote an instructive and productive interchange among not only
CAD/DA/VLSI researchers and developers; vendors and users, but also a
variety of those scientists,engineers, and students who are interested
in theoretical issues on CAD/DA/VLSI.
Background:
ASP-DAC'95 is the first in a series of biennial international
conferences on Design Automation. Generally, CAD/DA activities in Asia
and South Pacific Region may be regarded as distinctive in that a
specific range of design tasks closely related to
fabrication/manufacturing, such as physical design, test design,
packaging design, etc., has been more active than an integrated set of
design tasks including high-level synthesis, logic synthesis,
siliconcompilation, etc. Thus the conference aims at providing the
Asian and South Pacific CAD/DA community with opportunities of basing
leading edge researches notonly on specific design concepts but also
on new aspects of approaches to integrated design concepts.
CHDL has been held every 2 years since 1973, rotating between
Europe, North America and Asia. Since 1981 it has been organized by
the IFIP Working Group 10.2 on System Description and Design Tools.
This forward-looking conference traces the progress in the design of
HDLs and the methodology surrounding their use.
VLSI'95 is the eighth in a seriesof biennial international
conferences on Very Large Scale Integration sponsored by IFIP TC 10
Working Group 10.5 (VLSI). This conference will cover all aspects of
the interaction between VLSI technologyand electronic system design.
Scope of the Conference:
The emphasis of ASP-DAC'95 will be placed on Physical Design,
Test Design, Synthesis, Manufacturing, Design Environments, Design
Methodology, User-Oriented Topics, and Theoretical Aspects of CAD/DA.
The emphasis of CHDL'95 will be placed on Formal Methods,
Verification, Hardware Description Languages, High-Level Synthesis,
System Design, Simulation and Modeling, Design Frameworks and Design
Environments.
The emphasis of VLSI'95 will be placed on the exchange of new
ideas on systems, circuits and device technologies to make long stride
up to the new century.
Exhibition:
An exhibition, EDA Technofair'95, sponsored by Electronics
Industries Association, Japan, will be held from Aug. 30 to Sept. 1,
in parallel with the conference, and will be open free ofcharge to all
attendees. Over 50 exhibitors are expected to participate with
specializing CAD/DA/CAE systems, hardware platform related products,
publications, and services. Please contact the Conference Secretariat
when requiring exhibition space.
Panels and Tutorials:
Panels and tutorialswill be organized during the Conference.
Suggestions are welcome and have to be addressed to the Conference
Secretariat no later than February 24, 1995.
Location:
The Conference and Exhibition will be held at the Nippon
Convention Center(NCC) located in "Makuhari Messe", Chiba Prefecture,
east of Tokyo, approximately 30 minutes drive by car from either
downtown Tokyo or Narita Airport. NCC isalso accessible by Japan
Railways(JR) Keiyo Line. It takes about 30 minutes from Tokyo Station
to Kaihin Makuhari Station, which is a few minutes walk away from NCC.
Deadlines and Key Dates:
Submission of Manuscript: Feb. 24, 1995
Notification of Acceptance: May 10,1995
Final Version of Manuscript: Jun. 15, 1995
Pre-Conference Tutorials: Aug. 29, 1995
Conference Sessions: Aug. 30 - Sept. 1, 1995
Exhibition: Aug. 30 - Sept. 1, 1995
Areas of Interest:
ASP-DAC'95
[A] Physical Design: analysis/simulation, analog/digital synthesis,
floorplanning and placement, global/detailed routing, module
generator and layoutsystems, high-speed and microwave DA, mathematics
for physical design,
[B] Test Design: fault mo deling and simulation, test generation, test
validation, design-for-testability, combinatorics for testdesign,
[C] Synthesis: high-level synthesis, logic synthesis, sequential
synthesis, asynchronous synthesis, technology mapping, combinatorics
for synthesis,
[D] Design Verification: functional verification, layout verification,
timing verification,p erformance verification,
[E] Manufacturing: technology CAD, DA for IC fabrication,CAM,
packaging CAD, multi-chip module: design and manufacturing,
[F] Design Environments: HDL-based design,design schemes and
databases, human factors inDA, frameworks, DA tools,
[G] Design Methodology: high performance design, DAfor ASIC,
hardware/software codesign, VLSI implementation: theory and practice,
[H] User-Oriented Topics: integrated usage of vendor tools, standards
issues: VHDL, Verilog HDL, UDL/I, CFI, and EDIF, silicon strategies:
FPGA, PLD, and ASIC, personal computer CAD
CHDL'95
[A] Formal Methods: formal systems for reasoning about hardware,
formal representation techniques, theoretical models,
characterization of synchrony/asynchrony, integrating formal systems
with CAD, hybrid formal systems,computer support of reasoning
processes, designcritical and safety-critical applications,
[B] Verification: automatic verification of hardware descriptions,
finitestate verification, language containment, model checking,
symbolic simulation, verification algorithms and computer
representations, general- purpose reasoning systems applied to
hardware (e.g. HOL, Nqthm, OBJ, etc.), design derivation (design by
transformation), proof management and human-interface issues,
reasoning about self-timed and reactive systems,examples and
benchmarks,
[C] Hardware Description Languages: syntax and semantics of HDLs, new
developments in language design, advances in the use of HDLs in
practice, graphicallanguages, issues in language standardization,
standard languages such as VHDL, Verilog, UDL/I, etc.,
[D] High-Level Synthesis: tools and algorithms for synthesis at higher
specification levels,expressing and using constraints,synthesis of
asynchronous systems,extensions to systems synthesis, testability
issues,
[E] System-Level Design: very high level specification techniques and
tools, codesign, embedded system design, modeling and simulation,
theoretical foundations, interfaces,
[F] Design Systems and Tools: CADframeworks, design environments,
hardware emulation, prototyping, tool integration, datamo deling and
data management,
[G] Design Analysis and Test: discrete simulation, simulation
languages, testing, timing and performance
VLSI'95
[A] VLSI Architecture: architectures of embedded systems, processor
architectures, parallel and array architectures, defect and fault
tolerant architectures, architectural support for operating systems
and languages, hardwarealgorithms, computer arithmetic, self timed
chips, architectures forrapid prototyping,
[B] Applications: signal and image processing, communications,
graphics, robotics, machine control, automotive applications, neural
networks, rapid prototyping, analog systems,
[C] Design and Test Technology: design for testability, design for
manufacturability, design for reliability, partitioning techniques
for systems and circuits, mixedanalog/digital design, mixed
hardware/software design, concurrent engineering,
[D] Implications of New Technologies: optical computing and
interconnections, bioelectronics, mechatronics,low temperature, low
voltage, multichip mo dules, 3-D devices, sensors and actors, display
devices, programmable devices, memory systems, high-performance
packaging and interconnections,
[E] Design Automation Tools: high level synthesis,logic synthesis,
layout synthesis, test generation, simulation, verification,
frameworks.
Submission of Papers:
Prospective authors are invited to submit to the Conference
Secretariat 6 copies of a draft paper in English, which satisfies
the following:
(1) The cover page should specify [i] submission to ASP-DAC'95 or
CHDL'95 or VLSI'95, [ii]title, [iii] authors and affiliation, [iv]
mailing address, phone No.,FAX No., and e-mail address of the contact
author, [v] a brief abstract describing the work, [vi] at least three
keywords which can specify typically the contents of the work.
(2) The size of a sheet is A4 or 8.5" 11", and the length should not
exceed 20 pages excluding the cover page.
(3) The technical expositions should be directed to a specialist and
should include an introduction understandable to a nonspecialist that
describes the problem studiedand the results achieved, focusing on the
important ideas andtheir significance.
Any paper that deviates significantly from these guidances, or is not
received by the dead line, risks rejection without consideration of
its merits.
Awards:
Each of ASP-DAC'95/CHDL'95/VLSI'95 will offer awards for the best
papers selected by the Program Committee.
Proceedings:
All papers of the three conferences will b eincluded in one volume.
Chairs:
General Chair Prof. Tatsuo Ohtsuki,
Waseda University, Japan
Program Chairs
ASP-DAC'95: Prof. Isao Shirakawa,
Osaka University, Japan
CHDL'95: Prof. Steven D.Johnson,
Indiana University, U.S.A.
VLSI'95: Prof. Wolfgang Rosenstiel,
University of Tubingen, Germany
Conference Secretariat:
ASP-DAC'95/CHDL'95/VLSI'95 Secretariat
Business Center for Academic Societies Japan
5-16-9 Honkomagome, Bunkyo-ku, Tokyo 113, JAPAN
TEL: +81-3-5814-5800
FAX: +81-3-5814-5823