16th DASC tutorial : VHDL CODE DESIGN and VERIFICATION TECHNIQUES

16th DASC tutorial : VHDL CODE DESIGN and VERIFICATION TECHNIQUES

Post by VhdlCoh » Sat, 23 Aug 1997 04:00:00



Below is a description of a tutorial that I'll be presenting on October
26, 1997 at the Hyatt Regency in Irvine, California (~60 mi from LAX).
See my web site    http://members.aol.com/vhdlcohen/vhdl     for :  
  - a complete description of the tutorials, file "tutorial.doc"
  - Registration form, file  "16DASC_r.doc
  - Complete program, file 16DASC.doc
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Tutorial 103:  VHDL CODE DESIGN and VERIFICATION TECHNIQUES
Description:  This tutorial emphasizes VHDL design and verification
techniques that are necessary to achieve reusable and synthesizable code.
The goals of these approaches are to minimize design costs and cycle time
by providing reusable and verifiable designs, and adapting these designs
to new environments.
Tutorial contents provide:  1) a review of VHDL in a reusable and
adaptable style; 2) a review of VHDL for synthesis; 3) design (functional)
 verification and regression techniques; 4) design approaches for minimum
impact to parts obsolescence; and 5) a complete design example.
Participants are expected to have some knowledge of VHDL.

Instructor:  Ben Cohen has an MSEE from USC and is a Scientist engineer at
Hughes Aircraft Company.  He has technical experience in digital and
analog hardware design, computer architecture, ASIC design, and synthesis.
 He used hardware description languages for the modeling of systems at
various modeling levels including statistical, instruction set
architecture, and synthesis.  Since 1990, he applied VHDL to model various
bus functional models of computer interfaces.  He recently authored two
VHDL books:  VHDL Coding Styles and Methodologies and VHDL Answers to
Frequently Asked Questions.  He was also involved on several hardware,
software, and firmware tasks for several microprocessor applications.  He
taught classes at USC and at Hughes on the application of microprocessors,
Pascal, and VHDL.