by About the Company
Synopsys, Inc. (NASDAQ:SNPS) develops, markets and supports high-level
design automation models and software for designers of integrated circuits
(ICs) and electronic systems. The company pioneered the commercial
development of synthesis technology, which serves as the foundation of the
company's high-level design methodology. Synopsys offers a comprehensive
set of synthesis, simulation, test, and design reuse solutions, which
support both Verilog HDL and VHDL.
Job Descriptions:
Sr. R & D Engineer - Modeling
Work with other to define and develop technology and tools for
representation and creation of static timing models for digital circuitry.
This technology will be incorporated in high-performance next generation
analysis, verification and design planning tools within a high-level design
environment. Experience: The candidate is expected to be proficient in C
or C++, UNIX, software engineering principles, and be familiar with CAE
databases, data structures and algorithms. The candidate should also have
good problem solving skills, an understanding of ASIC and VLSI design
issues and, be capable of taking well defined problems and solving them
with the minimum of supervision. Knowledge of delay calculation,
simulation, modeling and static timing technology is a plus. At least 3
years of experience in C-or C++, under UNIX. Experience in development of
large and complex software project (>50K) in C. Familiarity with ASIC
design issues and verification process. Education: BS/MSCS or BSEE/MSCS
with 4+ years of experience, or a Ph.D. in a relevant area.
Sr. R & D Engineer - Incremental Timing Engineer
Work with others to define and develop new features in an incremental
static timing engine to satisfy the emerging needs of next generation
design planning tools. Identify areas of improvement in the core timing
engine, and help with the productization of next generation products. Work
with other developers and application engineers to identify and develop
enhancements. Experience: At least 3 years of experience in C++ or C,
under UNIX or AIX. Experience in development of large and complex software
project (>50) in C with emphasis on advanced algorithms and data
structures. Familiarity with ASIC design issues and verification process.
Knowledge of modeling and static timing technology is a big plus. This
candidate should have storing software engineering backgrounds, and capable
of taking well defined problems and solving them with a minimum of
supervision (good problem solving skills). Familiarity with logic synthesis
and physical design tools is a big plus. Education: BS/MSCS or BSEE/MSCS
and 4+ years of experience.
Datapath Engineer
Will participate in the definition, implementation and delivery of next
generation products for optimization and layout of datapath architectures.
As part of the datapath team, candidate in this position will participate
in
developing new and revolutionary capabilities in this rapidly growing
segment of the EDA market. The successful candidate must have a strong
background in software engineering and working with complex software
systems. Candidate must be able to plan and develop independently as well
as contribute substantially to team direction. Knowledge of ASIC design,
layout issues and tools, and HDL synthesis are also a very important.
Experience: Experience in developing and maintaining complex software
systems in C or C++ (> 50K lines of code). Strong algorithm and data
structure skills. Strong debugging/analysis skills. Familiarity with
digital electronics and EDA. Education: M.S. or Ph.D. in EE or CS plus 4
years software experience B.S. in EE or CS plus 7 years of software
experience.
R&D Technical Leader, Logic Synthesis
Research and development of strategic logic synthesis technologies and
product features. Technology road map definition, system architecture and
software development. Candidate will act as technical project leader of
strategic logic synthesis projects to address next generation design
requirements. Drive adoption of new technologies from academia into logic
synthesis. Develop synthesis solutions for high performance and complex
designs. Experience: Excellent software skills and experience with
modern software development tools. EDA tool development experience,
strong knowledge of ASIC or custom VLSI design methodologies. Excellent
communication and teamwork skills. Education: BS/MS in CS/EE and 5 yr.
experience, or Ph.D. and 2 yr. experience.
Senior R&D Engineer: GL Placement
This senior engineer will be responsible for developing core physical
design software, involving state-of-the-art techniques. This work will
include specification, analysis, development and testing of key gate-level
floorplanning systems. The engineer may also work on the interface with
synthesis and timing analysis, including timing-driven placement and
re-optimization control. The individual is expected to serve as a resource
to Synopsys in the area of physical design. The engineer is expected to
specify, design, implement, document and test large, complex bodies of
software embodying complex structures and algorithms. The candidate must
clearly be committed to high quality in the operation of the software, and
the in quality of its results. S/he must have demonstrated faculty in
working in large, complex software systems involving many other developers.
The work will also involve project leadership. The engineer is expected
to identify the key project areas, resource requirements, and work out
detailed technical specifications with management and other interested
parties. Experience: The candidate should have deep experience building
and maintaining a successful physical design system. Experience should
include algorithm study/research, writing, reviewing, analyzing large
bodies of software, doing competitive analysis, and maintaining the system
in the face of customer feedback. The candidate should have hands-on
experience with one or more of the following: standard cell layout,
gate-array layout, embedded core layout, global/local routing, quadratic
optimization techniques, and compaction. Knowledge of C/C++ is important.
Education: A MS in Electrical Engineering or Computer Science, or
comparable work experience is required. A Ph.D. would be an advantage.
DCL Manager
You will be responsible for leading a team of engineers to develop and to
maintain timing calculation capability based on the DCL (Delay Calculation
Language) standard. The work will include: (1) recruiting a team of 3 - 5
engineers (2) providing primary technical guidance during the DCL project
planning, (3) leading the design of the software architecture and the
detailed technical implementation of the DCL capability, (4) performing
project management function, (5) working with external development partners
and standard organizations. Will require strong background in implementing
advanced delay calculation for ASIC EDA tools. Must be familiar with the
deep sub-micron technology trend. It is also desirable to have the
candidate with basic project planning skill. The qualified candidate is
expected to identify the key project areas, quantify resource requirements,
and work out detailed technical specifications with marketing, customers,
management and other interested parties. Experience: Must have experience
developing and/or supporting a commercial ASIC EDA system. This includes
writing, reviewing, analyzing large bodies of software, developing delay
calculation capability, doing competitive analysis, and maintaining the
system in the face of customer feedback. Applicable gate level timing
analysis experience is highly desirable Education: MS in EE or CS with 5
years related experience or comparable credential is required.
Links to Layout Manager
Synopsys is looking for an Engineering manager to come and join the Logic
Synthesis team and take ownership for research and new product development
in the area of links to layout tools and ?physical driven synthesis?. The
technology and product challenges are in how to merge the synthesis and
placement technologies/products such that synthesis can retain accurate
estimates for the nets in the design as well as doing a better job of
synthesizing for physical goals in addition to the more traditional logical
goals. The manager will also be managing a fast growing, high caliber R&D
team. Success in this role is critical to Synopsys maintaining it?s
dominance of the synthesis marketplace.
Experience: Demonstrated technical team leadership. At least 2 years
experience managing high-caliber software development teams. At least 5
years experience and knowledge in bringing EDA products to market.
(Having managed an algorithmically deep product such as P&R,
floorplanning, simulation, timing, etc. would be an advantage.) A strong
ASIC design background. Experience in floorplanning or P&R very important
Education: Candidate should have at least a MS in EE or CS.
SR R&D Engineer - Delay Calculation System (DCS)
You will be responsible for implementation of a new compiler for the OVI
Delay Calculation Language (DCL). This will include research of the
existing DCL specification and compiler software, defining architecture of
the new compiler, developing parser and C code generation from the DCL
source. The engineer will focus on the language compilation sub-system of
the new Synopsys Delay Calculation System (DCS). The work will involve
software system architecture design and code development. The engineer is
expected to specify, design, implement, document and test large, complex
software embodying state of the art compiler techniques. A complete
language compilation system including debugging utilities and application
methodology are expected as the result. Must be able to write/design
efficient software without significant supervision. Experience: The
candidate should have experience developing and/or supporting a commercial
programming language compiler/code-generation system. EDA tool development
experience is preferred but not essential. Experience should include
writing, reviewing, analyzing large bodies of software. A strong
background in UNIX, C, and related software development tools and process
is required. The preferred candidate should have optional experience with
one or more of the following: ASIC EDA tools and methodology, logic level
cell timing model, ASIC cell characterization & measurement, and circuit
design. Education: A MS in Electrical Engineering or Computer Science with
five years? related work experience, or comparable credential, is required
Senior R&D Engineer: XIG
Job Description
This engineer will be responsible for maintenance and implementation of the
Synopsys netlist and schematic interfaces to third party tools. The
person's duty including development of various readers and writers of
netlist languages, such as EDIF, TDL, and NDL. The Framework integration,
ie. Mentor Falcon interface, is also part of the duty.
The work will involve software system architecture design and code
development. The engineer is expected to specify, design, implement,
document and test large, complex bodies of software. He or she must be a
team player to work with many other developers of the Logic Synthesis and
Library Modeling teams. Interaction with third party partners is expected
during the course of development time. Must be able to work independently
and communicate accurately with co-workers. Must be self-motivated and able
to write/design efficient software without significant supervision.
Experience: The candidate should have experience developing and/or
supporting a commercial EDA system. Applicable delay calculation or static
timing analysis experience is highly desired for this position. Experience
should include writing, reviewing, analyzing large bodies of software. A
strong background in UNIX, C, and related software development tools and
process is required.
The preferred candidate should have optional experience with one or more of
the following: static timing analysis model, logic synthesis, and
gate-level simulation. Education: A MS/Ph.D. in Electrical Engineering
or Computer Science with five-year related work experience, or comparable
credential, is required.
Physical Design Engineer
Job Description
This senior engineer will play a key role in the development of a
floorplanning and physical design system. Tasks would include
specification, analysis, development, testing and qualification of new
software and enhancement of existing software. Tasks could include serving
as a liaison with various internal and external development groups.
Software projects will have both algorithmic (applications) and
infrastructure (data models, interfaces) aspects. A broad knowledge of
physical design software/ algorithms/ systems, and in depth knowledge of a
few specific areas is essential for this position. However, even more
important is a willingness and desire to tackle new areas and problems.
The function involves working at a senior level in a team that could be
spread over multiple sites. It also involves working in/with a large system
(>1M lines of code). The job demands a highly quality conscious individual,
in terms of software quality as well as in terms of quality of results
(competitiveness). The job also requires an ability to see projects through
to a successful conclusion. Experience: Experience in developing physical
design related software is required, in algorithmic areas as well as in
infrastructure (data models, integration) areas. Good knowledge of
physical design tools/ systems in general is also required. Education: BS
CS or EE required. MS or Ph.D. an advantage.
If interested in these positions please send your resume to:
Synopsys, Inc.,
700 East Middlefield Road, MS MV-B1
Attn: Cheryl Erickson, Dept. NN
Mountain View, Ca 94043-4033
Fax: 415-694-4054
E-mail in ASCII text: cher...@synopsys.com
An equal opportunity employer.