by About the Company
Synopsys, Inc. (NASDAQ:SNPS) develops, markets and supports high-level
design automation models and software for designers of integrated circuits
(ICs) and electronic systems. The company pioneered the commercial
development of synthesis technology, which serves as the foundation of the
company's high-level design methodology. Synopsys offers a comprehensive
set of synthesis, simulation, test, and design reuse solutions, which
support both Verilog HDL and VHDL.
About the Design Planning Group
The Design Planning Group is a newly formed growing Business Unit chartered
with delivering the best methodology and tools for the next generation of
IC Design. We will develop dramatically better solutions that speed new,
highly complex designs to market. Key areas of development will include
design planning, and static timing sign-off with close ties to current and
next generation synthesis tools.
Job Descriptions:
Sr. R & D Engineer - Modeling
Work with other to define and develop technology and tools for
representation and creation of static timing models for digital circuitry.
This technology will be incorporated in high-performance next generation
analysis, verification and design planning tools within a high-level design
environment. Experience: The candidate is expected to be proficient in C
or C++, UNIX, software engineering principles, and be familiar with CAE
databases, data structures and algorithms. The candidate should also have
good problem solving skills, an understanding of ASIC and VLSI design
issues and, be capable of taking well defined problems and solving them
with the minimum of supervision. Knowledge of delay calculation,
simulation, modeling and static timing technology is a plus. At least 3
years of experience in C-or C++, under UNIX. Experience in development of
large and complex software project (>50K) in C. Familiarity with ASIC
design issues and verification process. Education: BS/MSCS or BSEE/MSCS
with 4+ years of experience, or a Ph.D. in a relevant area.
Sr. R & D Engineer - Core Timing
Work with others to develop new algorithms, refine existing algorithms and
data structures for a state-of-the-art static timing analysis tools.
Develop novel approaches in identifying timing problems within the context
of static timing analysis in deep submicron technologies. Identify and
develop new features to address these emerging needs. Experience: The
candidate is expected to be proficient in C or C++, UNIX, strong data
structures and algorithms. The candidate should also have good
communication skills and a good understanding of ASIC and VLSI design
issues. Knowledge of static timing technology is a big plus. Candidate
should have a strong software background, and capable of taking well
defined problems and solving them with the minimum of supervision (good
problem solving skills). Having worked in the area of timing analysis is
an advantage, but not essential. Experience in development of large and
complex software project (>50K lines) in C or C++ with emphasis on data
structures and algorithms. Experience in developing software in a team,
preferably in VLSI CAD tool development. Education: BS/MSCS or BSEE/MSCS
and 4+ years of experience, or a Ph.D. in a relevant area.
Sr. R & D Engineer - Project Lead - GUI
Lead technical design and development of the user interface for next
generation chip-level static timing analyzer and other related tools. The
user interface provides intuitive and efficient textual and graphical
interfaces to capture commands and annotations, customize the result and
analysis to generate reports, display reports in both graphical and textual
form, and enable users to interact with both the analysis run and the
results. Experience: The candidate is expected to be proficient in C or
C++, UNIX, software engineering principles, and to have hands-on experience
with the design and development of sophisticated graphical user interfaces
for engineering tools. The candidate should also have good problem solving
skills, communication and leadership skills. The candidate is expected to
have 6+ years of experience in SW development with at least 3 years
experience in GUI development using X/Motif and Windows UI and MFC. The
candidate should have experience in developing large and complex software
project (>50K) in a team, past project leadership experience, and have
strong software engineering skills. Good project planning, communication
and interpersonal skills are required. Familiarity with one or more of the
following is a plus: static timing analysis, logic simulation,
floorplanning and physical design, and principles of digital circuit
design. Education: BS/MSCS or BSEE/MCCS with 6+ years of experience with
at least 3 years experience in GUI development using X/Motif or Windows UI
and MFC.
Sr. R & D Engineer - Incremental Timing Engineer
Work with others to define and develop new features in an incremental
static timing engine to satisfy the emerging needs of next generation
design planning tools. Identify areas of improvement in the core timing
engine, and help with the productization of next generation products. Work
with other developers and application engineers to identify and develop
enhancements. Experience: At least 3 years of experience in C++ or C,
under UNIX or AIX. Experience in development of large and complex software
project (>50) in C with emphasis on advanced algorithms and data
structures. Familiarity with ASIC design issues and verification process.
Knowledge of modeling and static timing technology is a big plus. This
candidate should have storing software engineering backgrounds, and capable
of taking well defined problems and solving them with a minimum of
supervision (good problem solving skills). Familiarity with logic synthesis
and physical design tools is a big plus. Education: BS/MSCS or BSEE/MSCS
and 4+ years of experience.
Sr. R & D Engineer - DB & Interfaces
Technical lead in the development of data bases and interfaces for next
generation floorplanning and timing analysis tools for deep sub-micron
design. This engineer will be part of the Floorplanning Product Team.
This team is chartered to provide tools for design of large Structured
Custom and Application Specific Integrated Circuits to create high quality
designs faster, with efficient links to synthesis. This engineer will play
a lead role in defining data models and external tool interfaces, and
coordinating their implementation by engineers within the group, in other
business units and with Synopsys development partners. Experience: At
least 6 years of experience in using C/C++ and UNIX. Experience in
development of large and complex software projects in C/C++, with emphasis
on physical data structures and libraries. At least 4 years industrial
experience. Experience in developing software in a team, preferably in a
VLSI CAD tool development. Good understanding of physical design issues,
strong software engineering skills. Excellent communication (both written
and oral), project planning and interpersonal skills. Pluses: Familiarity
with logic synthesis, high-level design, static timing verifiers, ASIC
flows. Education: MSCS or MSEE and 6+ years of experience in a relevant
area, or equivalent.
Staff R & D Engineer - Development & Test (Release, Conf Mgmt)
Develop and administer a reliable software development and test environment
for the Design Planning business unit. Coordinate and schedule the hand
off of software from R&D to Release Engineering. Work with an external
software development partner to coordinate multi-site development, and to
converge upon a single system for software development, test and release.
This engineer will be part of a team chartered to provide chip-level tools
which bridge the gap between synthesis and detailed physical design, to
enable the rapid design of large high-performance ASICs. Experience: The
candidate should have several years of experience in software development,
test and release in a UNIX environment. The candidate should be
comfortable with sophisticated makefiles and shell scripts, C programming,
and be familiar with tools for source code control and configuration
management. Excellent coordination, planning and communication skills are
required. The candidate should be self-directed and able to learn
independently. Pluses: C++, software porting, familiarity with RS-6000,
ASIC EDA experience with synthesis or physical tools. Education: MS/MS CS
(or in EE with software experience.)
Corporate Applications Engineer
The CAE will be involved in developing and bringing to production our
static timing analysis tool to ensure that it fits in with our Chip Level
Methodology and fully meets the requirements for chip level sign-off. As
part of this role the CAE will be expected to work closely with both
internal and external development particularly with groups such as the Chip
Level Timing, Floorplanning and Logic Synthesis groups along with the
customers and our semiconductor partners. Other key responsibilities
include fully supporting the tool for and at production release by
methodology development and validation, implementation testing, demo
development, documentation, generation of training material, strategic
customer support and training of the field AE's. Experience: 6+ years as
an Application Engineer supporting ASIC designer with particular emphasis
on static timing analysis, excellent communication, teamwork, and customer
interaction skills are required. A strong background in gate-array and
standard cell ASIC design is a plus as well as a good knowledge of
High-Level Design Methodologies and familiarity in floorplanning, place and
route. Knowledge of third party tools such as MOTIVE or PEARL is a
distinct advantage. Education: MS/BS in EE.
Senior R&D Engineer: GL Placement
This senior engineer will be responsible for developing core physical
design software, involving state-of-the-art techniques. This work will
include specification, analysis, development and testing of key gate-level
floorplanning systems. The engineer may also work on the interface with
synthesis and timing analysis, including timing-driven placement and
re-optimization control. The individual is expected to serve as a resource
to Synopsys in the area of physical design. The engineer is expected to
specify, design, implement, document and test large, complex bodies of
software embodying complex structures and algorithms. The candidate must
clearly be committed to high quality in the operation of the software, and
the in quality of its results. S/he must have demonstrated faculty in
working in large, complex software systems involving many other developers.
The work will also involve project leadership. The engineer is expected
to identify the key project areas, resource requirements, and work out
detailed technical specifications with management and other interested
parties. Experience: The candidate should have deep experience building
and maintaining a successful physical design system. Experience should
include algorithm study/research, writing, reviewing, analyzing large
bodies of software, doing competitive analysis, and maintaining the system
in the face of customer feedback. The candidate should have hands-on
experience with one or more of the following: standard cell layout,
gate-array layout, embedded core layout, global/local routing, quadratic
optimization techniques, and compaction. Knowledge of C/C++ is important.
Education: A MS in Electrical Engineering or Computer Science, or
comparable work experience is required. A Ph.D. would be an advantage.
If interested in these positions please send your resume to:
Synopsys, Inc.,
700 East Middlefield Road, MS MV-B
Attn: Cheryl Erickson, Dept. NN
Mountain View, Ca 94043-4033
Fax: 415-694-4331
E-mail in ASCII text: cher...@synopsys.com
An equal opportunity employer.