In Search of Graphical VHDL Code Generators for FPGA Design

In Search of Graphical VHDL Code Generators for FPGA Design

Post by Lance Gi » Wed, 24 Jan 1996 04:00:00



I'm looking for opinions and feedback regarding any of the VHDL code
generators commercially available, such as those from Escalade, iLogix,
Mentor, R-Active, Speed Electronic, Summit Design, Vista Tech, and
"Shrink Wrap" vendors like Data IO and Viewlogic

We're trying to build a design environment, primarily targetting Xilinx,
that will allow us to mix schematics and generated VHDL. Initial designs
would have some FSM's and run 2K-12K gates. The ability to accommodate
VHDL newbies and incrementally gain VHDL experience is a plus.

Any comments you might like to share concerning your experiences/opinions/ideas
would be greatly appreciated, posted in public or private. Thanks,

____________________________________________________________________________

Lance Gin                                              "off the keyboad
Delco Systems - GM/Hughes Electronics                   over the bridge,
OFC: 805.961.7737  FAX: 805.961.7329                    through the gateway,

____________________________________________________________________________

 
 
 

In Search of Graphical VHDL Code Generators for FPGA Design

Post by Brian Child » Thu, 25 Jan 1996 04:00:00



writes

>I'm looking for opinions and feedback regarding any of the VHDL code
>generators commercially available, such as those from Escalade, iLogix,
>Mentor, R-Active, Speed Electronic, Summit Design, Vista Tech, and
>"Shrink Wrap" vendors like Data IO and Viewlogic

>We're trying to build a design environment, primarily targetting Xilinx,
>that will allow us to mix schematics and generated VHDL. Initial designs
>would have some FSM's and run 2K-12K gates. The ability to accommodate
>VHDL newbies and incrementally gain VHDL experience is a plus.

>Any comments you might like to share concerning your experiences/opinions/ideas
>would be greatly appreciated, posted in public or private. Thanks,

>____________________________________________________________________________

>Lance Gin                                              "off the keyboad
>Delco Systems - GM/Hughes Electronics                   over the bridge,
>OFC: 805.961.7737  FAX: 805.961.7329                    through the gateway,

>____________________________________________________________________________

You should also take a look at FlowHDL from Knowledge Based Silicon 803-
779-2504. It's lower cost (at least 2:1), easy to use, produces the
smallest synthsised implementation and readable code.

If your looking for points to evaluate against I would sugest some of
the following:-

1. Look closely at the code produced. You cannot get away from debuging
the machine generated code. If it is not readable you will have a
problem.

2. Make sure you synthesise the generated code. Sounds obvious but many
people I've talked to have skipped this step (top save time). The tools
I am familiar with produce *very* different gate counts, in some cases
as much as 3:1.

3. Ease of use. Obvious again. Some of the more 'pretty' tools look
great when demo'd but you need to spend some time to become as familiar
with the tool as the person giving the demo. This learning curve is
typically required for each project. The amount of time, during a design
cycle, spent using these tools is typically less than 1/3. During the
remainging 2/3 you will forget a lot...

These are just a few key pointers. If you would like some more send me a
private mail.

I have to state a vested interest here, as our company represents
flowHDL in the UK, *BUT* I feel the things to look out for, listed
above, are not biased. I'll leave you to be the judge.

Happy evaluating...

--
Brian Childs - VIZEF Limited

 
 
 

1. Simulating large VHDL design (FPGA backannotated)

Hi everybody,

I just ran into a problem that left me swinging in the breeze ...
If anybody could give me a hint or point me to a solution, I'd be
really happy.

Now the Problem:

I have a VHDL design targeted for a Altera FLEX FPGA (10K50).
I have it compiled with the Altera Tools and now want to do
a simulation with the actual timing values (post place-and-
route).
With the Altera SW, there are 2 possibilities to do that:
(A) you can get a VHDL-file which contains *everything*, including
    delays;
(B) you can use a SDF-file in combination with an Altera-provided
    VITAL-Library and an appropriate VHDL-netlist.

Now, doing this, I get a 2.4 MB VHDL-file in case (A), and even
bigger files for (B): 3.4 MB VHDL, ~4 MB SDF.

When I try to simulate these designs (Synopsys VSS), first everything
looks good, but when I try to set a trace (view a waveform), the
simulator gets to work (on what I don't know) and won't stop and
won't react to anything (at least for the 4 hours I had the patience
to wait).

OK, then I figured that this VHDL design simply was too large for
the *interpreted* VHDL-simulator from Synopsys and hence tried to
analyze the VHDL for the "compiled" mode. This took about 3 hours
(yes, only analyze & compile) before the job ran out of memory and
aborted. Oh, I was running it on a UltraSparc with 600 MB physical
memory and about 1.2 Gig of swap space ... wouldn't know where to
find a bigger machine here at the institute.

Now, what to do?
I hope that there are some folks who had similar problems and solved
them. After all, a "post-layout" simulation of a complete design
in a programmable device isn't so terribly unusual, no?

Looking forward to any ideas!

Yours, Georg.

--
All opinions expressed are mine, not my employers'.

######  #   #   #    #  ###  Georg Diebel
  #  #  ## ##   #    # #     Institute for Integrated Circuits
  #  #  # # #   #    #  ##   Technical University of Munich

  #  ####   #   #### # ###   Phone 0049-89-289-28578

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