We install a cadecne in a sun work station
But I don't know how to simuate a vhdl code.
Please help me.
Thank you for reading this question.
University of Newcastle Elec & Elec Eng.
For a course i am planing i need an example of a difference between
vhdl code and synthesis result, which does not create latch's,
use variable, or report warnings in synthesis tools.
Vlsi Design Eng.