Simulating large VHDL design (FPGA backannotated)

Simulating large VHDL design (FPGA backannotated)

Post by Georg Diebe » Fri, 11 Jul 1997 04:00:00



Hi everybody,

I just ran into a problem that left me swinging in the breeze ...
If anybody could give me a hint or point me to a solution, I'd be
really happy.

Now the Problem:

I have a VHDL design targeted for a Altera FLEX FPGA (10K50).
I have it compiled with the Altera Tools and now want to do
a simulation with the actual timing values (post place-and-
route).
With the Altera SW, there are 2 possibilities to do that:
(A) you can get a VHDL-file which contains *everything*, including
    delays;
(B) you can use a SDF-file in combination with an Altera-provided
    VITAL-Library and an appropriate VHDL-netlist.

Now, doing this, I get a 2.4 MB VHDL-file in case (A), and even
bigger files for (B): 3.4 MB VHDL, ~4 MB SDF.

When I try to simulate these designs (Synopsys VSS), first everything
looks good, but when I try to set a trace (view a waveform), the
simulator gets to work (on what I don't know) and won't stop and
won't react to anything (at least for the 4 hours I had the patience
to wait).

OK, then I figured that this VHDL design simply was too large for
the *interpreted* VHDL-simulator from Synopsys and hence tried to
analyze the VHDL for the "compiled" mode. This took about 3 hours
(yes, only analyze & compile) before the job ran out of memory and
aborted. Oh, I was running it on a UltraSparc with 600 MB physical
memory and about 1.2 Gig of swap space ... wouldn't know where to
find a bigger machine here at the institute.

Now, what to do?
I hope that there are some folks who had similar problems and solved
them. After all, a "post-layout" simulation of a complete design
in a programmable device isn't so terribly unusual, no?

Looking forward to any ideas!

Yours, Georg.

--
All opinions expressed are mine, not my employers'.

######  #   #   #    #  ###  Georg Diebel
  #  #  ## ##   #    # #     Institute for Integrated Circuits
  #  #  # # #   #    #  ##   Technical University of Munich

  #  ####   #   #### # ###   Phone 0049-89-289-28578

 
 
 

Simulating large VHDL design (FPGA backannotated)

Post by Thomas Bern » Fri, 01 Aug 1997 04:00:00



> Hi everybody,

Hi too,

Quote:> Now the Problem:

> I have a VHDL design targeted for a Altera FLEX FPGA (10K50).

So far so good.

Quote:> When I try to simulate these designs (Synopsys VSS), first everything
> looks good, but when I try to set a trace (view a waveform), the
> simulator gets to work (on what I don't know) and won't stop and
> won't react to anything (at least for the 4 hours I had the patience
> to wait).

What do think about Hardware/Software-Cosimulation. The partitioning
your design to components for simulation at all and components for
emulation at a prototyping board coupled to a HDL-Simulator is up to you.
The sight to the emulator partition is as a HDL entity.
But now, you can achive a significant speed up depend on the design.

Quote:> OK, then I figured that this VHDL design simply was too large for
> the *interpreted* VHDL-simulator from Synopsys and hence tried to
> analyze the VHDL for the "compiled" mode. This took about 3 hours
> (yes, only analyze & compile) before the job ran out of memory and
> aborted. Oh, I was running it on a UltraSparc with 600 MB physical
> memory and about 1.2 Gig of swap space ... wouldn't know where to
> find a bigger machine here at the institute.

Our HW/SW-Cosimulation environment supports also the VSS from Synopsys.

Quote:> Now, what to do?

Have a look at http://www.eas.iis.fhg.de/sim/projects/dfg/welcome_de.html

Quote:> Looking forward to any ideas!

Hope this helps.

Yours,

Thomas

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1. In Search of Graphical VHDL Code Generators for FPGA Design

I'm looking for opinions and feedback regarding any of the VHDL code
generators commercially available, such as those from Escalade, iLogix,
Mentor, R-Active, Speed Electronic, Summit Design, Vista Tech, and
"Shrink Wrap" vendors like Data IO and Viewlogic

We're trying to build a design environment, primarily targetting Xilinx,
that will allow us to mix schematics and generated VHDL. Initial designs
would have some FSM's and run 2K-12K gates. The ability to accommodate
VHDL newbies and incrementally gain VHDL experience is a plus.

Any comments you might like to share concerning your experiences/opinions/ideas
would be greatly appreciated, posted in public or private. Thanks,

____________________________________________________________________________

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Delco Systems - GM/Hughes Electronics                   over the bridge,
OFC: 805.961.7737  FAX: 805.961.7329                    through the gateway,

____________________________________________________________________________

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