We are currently looking for a code coverage tool, which is able to handle
blocks designed with schematic entry. This is probably not possible for the
schematic design itself, however for the synthesized design it should show
which gates were driven.
I would greatly appreciate, if you could point out one or more code coverage
tools that would do this job best or which deliver the best value for their
So far, we used "Nccov" which came with the latest release of the NC_Verilog
simulator, however it neither handles primitive instantiations nor assign