Example of difference between vhdl code and synthesis

Example of difference between vhdl code and synthesis

Post by nitzan poylit » Mon, 01 Feb 1999 04:00:00

For a course i am planing i need an example of a difference between
vhdl code and synthesis result, which does not create latch's,
use variable, or report warnings in synthesis tools.


Nitzan Poylitz
Vlsi Design Eng.


1. VHDL code for synthesis

* My tool is Synopsys 3.4 Design Analyzer

* My target is (for now)  Xilinx XC4000-series

* My question is: How do I code the following behaviour for synthesis?

I want a parallell loadable, seriall sending component with
fixed number of bits and a trigger signal.

if (CLOCK'event and CLOCK='1') then

        if (LOAD='1') then

                load the parallel data and the headerbits;

        if (SEND_FR='1') then

                send one frame of 37 bits (data + some header);
                one bit for every positiv clock edge;

        end if;
end if;

Design Analyzer does not allow wait on CLOCK mixed with
a process sensitivity list.
I have a working modell of this with 1 shifting process and
1 counter process with a start-stop signal between them, but
I want to do it in 1 process with some kind of loop maybe.

Any suggestions?

Magnus Larsson____________________Research Engineer________________

Halmstad University               Phone: +46 35167383
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