* My tool is Synopsys 3.4 Design Analyzer
* My target is (for now) Xilinx XC4000-series
* My question is: How do I code the following behaviour for synthesis?
I want a parallell loadable, seriall sending component with
fixed number of bits and a trigger signal.
if (CLOCK'event and CLOCK='1') then
if (LOAD='1') then
load the parallel data and the headerbits;
if (SEND_FR='1') then
send one frame of 37 bits (data + some header);
one bit for every positiv clock edge;
Design Analyzer does not allow wait on CLOCK mixed with
a process sensitivity list.
I have a working modell of this with 1 shifting process and
1 counter process with a start-stop signal between them, but
I want to do it in 1 process with some kind of loop maybe.
Magnus Larsson____________________Research Engineer________________
Halmstad University Phone: +46 35167383
P.O.Box 823 Fax: +46 35120348
S-301 18 Halmstad, SWEDEN http://www.hh.se/cca.html