VHDL code for synthesis

VHDL code for synthesis

Post by Magnus Larsso » Thu, 06 Jun 1996 04:00:00



* My tool is Synopsys 3.4 Design Analyzer

* My target is (for now)  Xilinx XC4000-series

* My question is: How do I code the following behaviour for synthesis?

I want a parallell loadable, seriall sending component with
fixed number of bits and a trigger signal.

if (CLOCK'event and CLOCK='1') then

        if (LOAD='1') then

                load the parallel data and the headerbits;

        if (SEND_FR='1') then

                send one frame of 37 bits (data + some header);
                one bit for every positiv clock edge;

        end if;
end if;

Design Analyzer does not allow wait on CLOCK mixed with
a process sensitivity list.
I have a working modell of this with 1 shifting process and
1 counter process with a start-stop signal between them, but
I want to do it in 1 process with some kind of loop maybe.

Any suggestions?

Magnus Larsson____________________Research Engineer________________

Halmstad University               Phone: +46 35167383
P.O.Box 823                       Fax:   +46 35120348
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VHDL code for synthesis

Post by Mark Lancast » Thu, 06 Jun 1996 04:00:00



>* My question is: How do I code the following behaviour for synthesis?

>I want a parallell loadable, seriall sending component with
>fixed number of bits and a trigger signal.

>if (CLOCK'event and CLOCK='1') then

>    if (LOAD='1') then

>            load the parallel data and the headerbits;

>    if (SEND_FR='1') then

>            send one frame of 37 bits (data + some header);
>            one bit for every positiv clock edge;

>    end if;
>end if;

>Design Analyzer does not allow wait on CLOCK mixed with
>a process sensitivity list.
>I have a working modell of this with 1 shifting process and
>1 counter process with a start-stop signal between them, but
>I want to do it in 1 process with some kind of loop maybe.

This isn't fully fleshed out, but it will show you how to do it:

par_2_ser: process (CLOCK, RESET)
begin
   if (RESET = '0') then
      REGISTER <= (others => '0');
   else if (CLOCK'event and CLOCK='1') then
      if (LOAD='1') then
         REGISTER <= PARALLEL_INPUT;
      end if;
      if (SEND_FR='1') then
         SERIAL_OUTPUT <= REGISTER(0);
         REGISTER(36) <= '0';
         REGISTER(35 downto 0) <= REGISTER(36 downto 1);
      end if;
   end if;
end process par_2_ser;

--
Mark Lancaster


 
 
 

VHDL code for synthesis

Post by Dan Prysb » Thu, 13 Jun 1996 04:00:00




>>* My question is: How do I code the following behaviour for synthesis?

>>I want a parallell loadable, seriall sending component with
>>fixed number of bits and a trigger signal.
-snip-
>This isn't fully fleshed out, but it will show you how to do it:

>par_2_ser: process (CLOCK, RESET)
>begin
>   if (RESET = '0') then
>      REGISTER <= (others => '0');
>   else if (CLOCK'event and CLOCK='1') then
>      if (LOAD='1') then
>         REGISTER <= PARALLEL_INPUT;
>      end if;
>      if (SEND_FR='1') then
>         SERIAL_OUTPUT <= REGISTER(0);
>         REGISTER(36) <= '0';
>         REGISTER(35 downto 0) <= REGISTER(36 downto 1);
>      end if;
>   end if;
>end process par_2_ser;

One potential problem is:
Both "if" statements could be true at the same time
and there is no priority so both conflicting register assignments
are attempted.
Should cover all combinations of LOAD and SEND_FR such that
only one register assignment is followed.
Maybe use "if" and "elsif" or "case CONTROL" where CONTROL
is an array of LOAD and SEND_FR.

Dan Prysby

 
 
 

VHDL code for synthesis

Post by Jan Decaluw » Fri, 14 Jun 1996 04:00:00



> Correct me if I'm wrong, but wouldn't it be the case that the final
> assignment to REGISTER would have priority over all previous assignments, as
> the signal will be assigned a value only when the process suspends.

> Roy

Absolutely right. There is no problem whatsoever with this code.
It's nice synchronous logic making use of the "pseudo-procedural"
behavior of signal assignments within a process to describe
a logical priority.

Regards, Jan

--
===================================================================
Jan Decaluwe              ===              Easics               ===
Design Manager            ===  VHDL-based ASIC design services  ===
Tel: +32-16-298 400          ===================================
Fax: +32-16-298 319         Kapeldreef 60, B-3001 Leuven, BELGIUM

 
 
 

VHDL code for synthesis

Post by R.G.Mo » Fri, 14 Jun 1996 04:00:00




: >>* My question is: How do I code the following behaviour for synthesis?
: >>
: >>I want a parallell loadable, seriall sending component with
: >>fixed number of bits and a trigger signal.
: -snip-
: >This isn't fully fleshed out, but it will show you how to do it:
: >
: >par_2_ser: process (CLOCK, RESET)
: >begin
: >   if (RESET = '0') then
: >      REGISTER <= (others => '0');
: >   else if (CLOCK'event and CLOCK='1') then
: >      if (LOAD='1') then
: >         REGISTER <= PARALLEL_INPUT;
: >      end if;
: >      if (SEND_FR='1') then
: >         SERIAL_OUTPUT <= REGISTER(0);
: >         REGISTER(36) <= '0';
: >         REGISTER(35 downto 0) <= REGISTER(36 downto 1);
: >      end if;
: >   end if;
: >end process par_2_ser;

: One potential problem is:
: Both "if" statements could be true at the same time
: and there is no priority so both conflicting register assignments
: are attempted.
: Should cover all combinations of LOAD and SEND_FR such that
: only one register assignment is followed.
: Maybe use "if" and "elsif" or "case CONTROL" where CONTROL
: is an array of LOAD and SEND_FR.

: Dan Prysby

Correct me if I'm wrong, but wouldn't it be the case that the final
assignment to REGISTER would have priority over all previous assignments, as
the signal will be assigned a value only when the process suspends.

Roy

 
 
 

VHDL code for synthesis

Post by Dan Prysb » Fri, 14 Jun 1996 04:00:00




-snip-

>: One potential problem is:
>: Both "if" statements could be true at the same time
>: and there is no priority so both conflicting register assignments
>: are attempted.
>: Should cover all combinations of LOAD and SEND_FR such that
>: only one register assignment is followed.
>: Maybe use "if" and "elsif" or "case CONTROL" where CONTROL
>: is an array of LOAD and SEND_FR.

>: Dan Prysby

>Correct me if I'm wrong, but wouldn't it be the case that the final
>assignment to REGISTER would have priority over all previous assignments, as
>the signal will be assigned a value only when the process suspends.

You are not "wrong" but what I'm pointing out is a possible
difference in pure VHDL code simulation and synthesized circuit
operation.
I have seen problems with VHDL code not completely specifying
operation, thus leaving it to the code simulator in one case
and the synthesizer in the other case.
Clear?
I will try to run a test through Synopsys to see if it can resolve
the D input logic and sees what all 4 combinations of LOAD and SEND_FR
do.
Alos, different synthesis algorithms may produce different logic
if not completely specified.
In short, it's risky for synthesis.

Dan Prysby

 
 
 

VHDL code for synthesis

Post by Dan Prysb » Fri, 14 Jun 1996 04:00:00





>-snip-
>I will try to run a test through Synopsys to see if it can resolve
>the D input logic and sees what all 4 combinations of LOAD and SEND_FR
>do.

-snip-

I have run a test through Synopsys:
Synopsys will generate 2 muxes.
The first mux, controlled by LOAD, feeds the second mux controlled by
SEND_FR, which feeds the D input of the register.
So SEND_FR = 1 will override LOAD for Synopsys v3.3b.
I still maintain synthesis for incompletely specified code
can be risky, it's a good thing to keep in mind.
Know what your synthesizer might do.
Code vs circuit simulations might differ.
Synopsys usually gives warnings for problematic code.
Note: many books deal with VHDL but not in a restricted manner
required by Synopsys.

Dan Prysby

 
 
 

VHDL code for synthesis

Post by Jan Decaluw » Fri, 14 Jun 1996 04:00:00





> -snip-

> >: One potential problem is:
> >: Both "if" statements could be true at the same time
> >: and there is no priority so both conflicting register assignments
> >: are attempted.
> >: Should cover all combinations of LOAD and SEND_FR such that
> >: only one register assignment is followed.
> >: Maybe use "if" and "elsif" or "case CONTROL" where CONTROL
> >: is an array of LOAD and SEND_FR.

> >: Dan Prysby

> >Correct me if I'm wrong, but wouldn't it be the case that the final
> >assignment to REGISTER would have priority over all previous assignments, as
> >the signal will be assigned a value only when the process suspends.

> You are not "wrong" but what I'm pointing out is a possible
> difference in pure VHDL code simulation and synthesized circuit
> operation.

If that happens for this type of description, there is only one
possible conclusion: the synthesis tool has a bug. There is no
fundamental problem. It's simply synchronous logic with logical
priorities.

Quote:> I have seen problems with VHDL code not completely specifying
> operation, thus leaving it to the code simulator in one case
> and the synthesizer in the other case.
> Clear?

Problems occur when trying to synthesize level-sensitive sequential
logic (latches) but not with edge-triggered logic as in this case.

Quote:> I will try to run a test through Synopsys to see if it can resolve
> the D input logic and sees what all 4 combinations of LOAD and SEND_FR
> do.

It will work.

Quote:> Alos, different synthesis algorithms may produce different logic
> if not completely specified.

The details of the logic may be different but the behavior is
unambigously specified and can always be cleanly synthesized.

Quote:> In short, it's risky for synthesis.

Again, a description of edge-triggered logic isn't.

Quote:

> Dan Prysby

--
===================================================================
Jan Decaluwe              ===              Easics               ===
Design Manager            ===  VHDL-based ASIC design services  ===
Tel: +32-16-298 400          ===================================
Fax: +32-16-298 319         Kapeldreef 60, B-3001 Leuven, BELGIUM

 
 
 

VHDL code for synthesis

Post by Wolfgang Eck » Sat, 15 Jun 1996 04:00:00


Please consider in your discussion about registers that "REGISTER"
is a reserver word in VHDL. The code shown in the discussion can not
be abalyzed!!

Wolfgang

 
 
 

VHDL code for synthesis

Post by Paul J Menchini - Menchini and Associat » Sat, 15 Jun 1996 04:00:00




: >-snip-

: >I will try to run a test through Synopsys to see if it can resolve
: >the D input logic and sees what all 4 combinations of LOAD and SEND_FR
: >do.
: -snip-

: I have run a test through Synopsys:
: Synopsys will generate 2 muxes.
: The first mux, controlled by LOAD, feeds the second mux controlled by
: SEND_FR, which feeds the D input of the register.
: So SEND_FR = 1 will override LOAD for Synopsys v3.3b.
: I still maintain synthesis for incompletely specified code
: can be risky, it's a good thing to keep in mind.
: Know what your synthesizer might do.
: Code vs circuit simulations might differ.
: Synopsys usually gives warnings for problematic code.
: Note: many books deal with VHDL but not in a restricted manner
: required by Synopsys.

The semantics of the example are clear--this is what the simulator does.
However, if the synthesizer doesn't do the same, then....

Of course, one must know and work with the limits of one's tools, which is
Dan's point.

Paul

--

Menchini & Associates | voice: 919-990-9506    | "Se tu sarai solo,
2 Davis Dr./POB 13036 | pager: 800-306-8494    |  tu sarai tutto tuo."
RTP, NC  27709-3036   | fax:   919-990-9507    |        -- Leonardo Da Vinci

 
 
 

VHDL code for synthesis

Post by Aurelio Mont » Sat, 15 Jun 1996 04:00:00


I'd like to add something to the discussion

: >par_2_ser: process (CLOCK, RESET)
: >begin
: >   if (RESET = '0') then
: >      REGISTER <= (others => '0');
: >   else if (CLOCK'event and CLOCK='1') then
: >      if (LOAD='1') then
: >         REGISTER <= PARALLEL_INPUT;
: >      end if;
: >      if (SEND_FR='1') then
: >         SERIAL_OUTPUT <= REGISTER(0);
: >         REGISTER(36) <= '0';
: >         REGISTER(35 downto 0) <= REGISTER(36 downto 1);
: >      end if;
: >   end if;
: >end process par_2_ser;
:
: One potential problem is:
: Both "if" statements could be true at the same time
: and there is no priority so both conflicting register assignments
: are attempted.

You should consider this is a process: statements are executed
sequentially. Then the second REGISTER assignement definitely takes
priority over the first one.


Quote:> You are not "wrong" but what I'm pointing out is a possible
> difference in pure VHDL code simulation and synthesized circuit
> operation.
> I have seen problems with VHDL code not completely specifying
> operation, thus leaving it to the code simulator in one case
> and the synthesizer in the other case.
> Clear?

Yes , but could you precise why the code in question
is not completely specified ?

I understand a code is not completely specified when some outputs
are not defined for some input combinations (with Design Compiler
you must indicate that using something like "output <= '-'").

Looking at this case I can see outputs do not change under
some input combinations, which is quite different. You should get
some logic implementing an enable function around your flip-flops.

Regards

Aurelio Monti