SNUG '98 Call For Papers
WHAT: Eighth Annual Synopsys Users Group (SNUG '98)
WHEN: March 11th-13th
WHERE: Double Tree Inn, San Jose, CA (formerly the Red Lion Inn)
An Invitation to Contribute
SHARE Your Experiences!
The success of a user's group depends on the active participation of users
who are willing to share their experiences with others. If you have
information on High-Level Design methodology or experiences with Synopsys
tools that would be of interest to other users, you are encouraged to
present in one of the sessions described below.
Preliminary User Breakout Sessions
These sessions are always the hit of the conference. Hear Synopsys users'
experience on specific topics. Each user breakout session will consist of
three presentations, twenty-five minutes each, with another five minutes for
questions and answers. Preliminary topics include:
Strategies, experiences, and best practices for design productivity
with an emphasis on synthesis. Automation and Optimization
techniques for synthesis.
Verification strategies covering design for test and system-level
verification. Users share experiences in developing a test bed to
verify the combined hardware and software systems. Design for
test strategies for complex, large designs.
*Higher Levels of Abstraction / Behavi*Synthesis
This sessions covers real-world experiences in making the transition
to high-level design. Topics include the methodology for top-down
design, behavi*synthesis, & high-level techniques for DSP design.
*Deep Submicron / Large Designs
Concentrating on the unique challenges of submicron and large
designs. Sessions provide experience with automating scripts for
submicron, special techniques for managing wireloading,
floorplanning, and non-linear delay modeling.
This is a popular session that was added to SNUG last year to
address the increased effort to automate and extend the synthesis
process through scripting. The session includes case studies by
users that have taken advantage of the power of Make and Perl
drive synthesis iterations and to extend DC Shell.
Management of files and directory structures is a big key
toward design success. This session will explore approaches
or methods like MAKE used to manage the complex designs of today.
This session includes a practical methodology for design reuse
based on real-world experience. Issues and guidelines are explored.
This year a new session will be added that will focus directly on
synthesis of FPGAs. Tricks and techniques used for designing and
synthesizing FPGAs will be presented. Experiences with FPGA Express
will also be included.
To present your experiences with a contribution in an user session, please
forward a summary or brief description of your idea to the conference
will be notified of your acceptance shortly afterwards. A Technical
Committee member will work with each author to develop and review the paper
and presentation. Please review the Author's kit posted on the Synopsys
web site for details on paper format and structure.
Final drafts are due by January 5, 1998.
Final papers are due for publication in the SNUG proceedings by
February 2, 1998.
A Preliminary SNUG '98 Schedule
Wednesday, March 11th
Morning 1/2 day Tutorial Sessions
Afternoon Industry related Panel Discussion
Evening R&D*tail Party /Synopsys New
Thursday, March 12th
Morning Executive Status
Morning/Afternoon User Breakout Sessions
Evening Cocktail Party / Vendor Fair
Friday, March 13th
Morning 1/2 day Tutorial Sessions
Who to Contact
Should you wish to discuss your potential contribution, please feel free to
contact your local Synopsys applications engineering manager or the SNUG'98
Technical Committee via email at:
All email sent to this alias will be reflected to User Group Technical
Chairperson and the Technical Committee. These addresses are NOT for basic
information on attending the conference itself.
Don Mills, Renae Cunningham,
SNUG '98 User Chairman SNUG '98 Synopsys Program Manager
640 North 2200 West 700 E. Middlefield Road
MS F1-J12 Mtn. View, CA. 94043
Salt Lake City, UT Fax: 415-965-2539
Trapped trying to figure out a Synopsys bug? Want to hear how 5459 other
users dealt with it ? Then join the E-Mail Synopsys Users Group (ESNUG)!
/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - / - John Cooley, EDA & ASIC Design Consultant in Synopsys,
_] [_ Verilog, VHDL and numerous Design Methodologies.
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
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