Very Computer

1. VHDL semantics, is there a public domain vhdl parser, vhdl--verilog converter

Hi :

1. I am looking at some VHDL code that is synthesizable and accepted by Synopsis
synthesis. It has some outputs declared and initialized, as  in for eg.
out1 <= '0';   -- declared and initialized simulataneously
out2 <=1;
out3
.
.

case state IS
        WHEN IDLE => state <= busy;
                   out2 <= '0';
        WHEN BUSY => state <= idle;
                   out1 <= '1';

etc...

 Qa. If some output is not assigned to in the case state is statement does it take on its      
     old value.
 Qb. Secondly does synopsis synthesis generate latches for these outputs?

The problem I am trying to solve is take a VHDL description of a design and translate it
to Verilog. In Verilog outputs are normally declared as wires.

Q2. Is there a public domain VHDL parser? Is there a public domain VHDL to Verilog converter?

I would appreciate any help/information. Please email your responses to:

Thanks,
Sriram

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