sysPhysMemDesc (mmu) init problem with MPC860

sysPhysMemDesc (mmu) init problem with MPC860

Post by Lian » Thu, 26 Jun 2003 10:13:02



Hi,

I have a board running MPC860 with 64M of SDRAM.  Before we only used
16M, so the sysPhysMemDesc table entry looks like this

#define LOCAL_MEM_LOCAL_ADRS 0x00000000
#define LOCAL_MEM_SIZE 0x01000000
#define USER_RESERVED_MEM 0x00100000

PHYS_MEM_DESC sysPhysMemDesc [] =
{
    {
        (void *) LOCAL_MEM_LOCAL_ADRS,
        (void *) LOCAL_MEM_LOCAL_ADRS,
        LOCAL_MEM_SIZE-USER_RESERVED_MEM,
        VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE |
VM_STATE_MASK_CACHEABLE,
        VM_STATE_VALID      | VM_STATE_WRITABLE      |
VM_STATE_CACHEABLE
    },

    {
        (void *) (LOCAL_MEM_SIZE-USER_RESERVED_MEM),
        (void *) (LOCAL_MEM_SIZE-USER_RESERVED_MEM),
        USER_RESERVED_MEM,
        VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE |
VM_STATE_MASK_CACHEABLE,
        VM_STATE_VALID      | VM_STATE_WRITABLE      |
VM_STATE_CACHEABLE_NOT
    },
...

Quote:}

Now when I change the LOCAL_MEM_SIZE to 0x04000000, or even just
0x02000000, my board would have problem booting up, namely the SMC
UART port cannot process characters in the receive buffer (interrupt
is always pending as indicated in CIPR, but not processed).

I could break up the entry into smaller segment, as follows

#if 0 /* entry A */
    {
        (void *) 0x01000000,
        (void *) 0x01000000,
        0x00400000,      /*  */    
        VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE |
VM_STATE_MASK_CACHEABLE,
        VM_STATE_VALID      | VM_STATE_WRITABLE      |
VM_STATE_CACHEABLE_NOT
    },
    {
        (void *) 0x01400000,
        (void *) 0x01400000,
        0x00400000,      /*  */    
        VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE |
VM_STATE_MASK_CACHEABLE,
        VM_STATE_VALID      | VM_STATE_WRITABLE      |
VM_STATE_CACHEABLE_NOT
    },
#endif
#if 1 /* entry B */
    {
        (void *) 0x02000000,
        (void *) 0x02000000,
        0x00400000,      /*  */    
        VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE |
VM_STATE_MASK_CACHEABLE,
        VM_STATE_VALID      | VM_STATE_WRITABLE      |
VM_STATE_CACHEABLE_NOT
    },
    {
        (void *) 0x02400000,
        (void *) 0x02400000,
        0x00400000,      /*  */    
        VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE |
VM_STATE_MASK_CACHEABLE,
        VM_STATE_VALID      | VM_STATE_WRITABLE      |
VM_STATE_CACHEABLE_NOT
    },
#endif

enabling both entry A and B will have the same problem, but just
enabling either of them is fine.  It appears that I could only enable
a max of 24M without any problem.  I've tested the entire 64M of
memory with VisionProbe while the board is running in the original
setting and there's nothing wrong with the memory.

Please help!  Thanks.

Liang

 
 
 

sysPhysMemDesc (mmu) init problem with MPC860

Post by david lindaue » Thu, 26 Jun 2003 10:48:48


I don't know about the PPC... but some of the embedded chips have
relocatable peripherals.  It could be the address given to them by the
BSP conflicts with the memory...

David


> Hi,

> I have a board running MPC860 with 64M of SDRAM.  Before we only used
> 16M, so the sysPhysMemDesc table entry looks like this

> #define LOCAL_MEM_LOCAL_ADRS 0x00000000
> #define LOCAL_MEM_SIZE 0x01000000
> #define USER_RESERVED_MEM 0x00100000

> PHYS_MEM_DESC sysPhysMemDesc [] =
> {
>     {
>         (void *) LOCAL_MEM_LOCAL_ADRS,
>         (void *) LOCAL_MEM_LOCAL_ADRS,
>         LOCAL_MEM_SIZE-USER_RESERVED_MEM,
>         VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE |
> VM_STATE_MASK_CACHEABLE,
>         VM_STATE_VALID      | VM_STATE_WRITABLE      |
> VM_STATE_CACHEABLE
>     },

>     {
>         (void *) (LOCAL_MEM_SIZE-USER_RESERVED_MEM),
>         (void *) (LOCAL_MEM_SIZE-USER_RESERVED_MEM),
>         USER_RESERVED_MEM,
>         VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE |
> VM_STATE_MASK_CACHEABLE,
>         VM_STATE_VALID      | VM_STATE_WRITABLE      |
> VM_STATE_CACHEABLE_NOT
>     },
> ...
> }

> Now when I change the LOCAL_MEM_SIZE to 0x04000000, or even just
> 0x02000000, my board would have problem booting up, namely the SMC
> UART port cannot process characters in the receive buffer (interrupt
> is always pending as indicated in CIPR, but not processed).

> I could break up the entry into smaller segment, as follows

> #if 0 /* entry A */
>     {
>         (void *) 0x01000000,
>         (void *) 0x01000000,
>         0x00400000,      /*  */
>         VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE |
> VM_STATE_MASK_CACHEABLE,
>         VM_STATE_VALID      | VM_STATE_WRITABLE      |
> VM_STATE_CACHEABLE_NOT
>     },
>     {
>         (void *) 0x01400000,
>         (void *) 0x01400000,
>         0x00400000,      /*  */
>         VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE |
> VM_STATE_MASK_CACHEABLE,
>         VM_STATE_VALID      | VM_STATE_WRITABLE      |
> VM_STATE_CACHEABLE_NOT
>     },
> #endif
> #if 1 /* entry B */
>     {
>         (void *) 0x02000000,
>         (void *) 0x02000000,
>         0x00400000,      /*  */
>         VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE |
> VM_STATE_MASK_CACHEABLE,
>         VM_STATE_VALID      | VM_STATE_WRITABLE      |
> VM_STATE_CACHEABLE_NOT
>     },
>     {
>         (void *) 0x02400000,
>         (void *) 0x02400000,
>         0x00400000,      /*  */
>         VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE |
> VM_STATE_MASK_CACHEABLE,
>         VM_STATE_VALID      | VM_STATE_WRITABLE      |
> VM_STATE_CACHEABLE_NOT
>     },
> #endif

> enabling both entry A and B will have the same problem, but just
> enabling either of them is fine.  It appears that I could only enable
> a max of 24M without any problem.  I've tested the entire 64M of
> memory with VisionProbe while the board is running in the original
> setting and there's nothing wrong with the memory.

> Please help!  Thanks.

> Liang


 
 
 

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