C5410 Dual access operands

C5410 Dual access operands

Post by Christian Stur » Wed, 28 Feb 2001 18:36:47



Hi, I'm having problems using dual memory access operands on my TI C5410 (using
a TIGER 5410.

I'm trying the following:

MACSU *AR2, *AR3, A

Where ar2 and ar3 contain 0x04A4 and 0x04A5 (ie < 0x1fff and hence in dual
access memory according to the TI manual). This instruction gives strange
results (I tried 0+= 1*1 = FFFF7DDE ). I have tried calling functions in the TI
DSPLib (mul32) and this returned strange results as well. I have FRCT =1, SXM = 1
and OVA = 0. The only thing I can think of is that the memory is not operating
in dual access mode. Do I need to set up the DSP to enable the bottom 8K as dual
access ram. Does anyone have any other suggestions of why dual access operations
would not work?

Thanks.

--      Christian Sturt                                            

 
 
 

C5410 Dual access operands

Post by Randy Yate » Thu, 01 Mar 2001 12:47:32



> Hi, I'm having problems using dual memory access operands on my TI C5410 (using
> a TIGER 5410.

> I'm trying the following:

> MACSU *AR2, *AR3, A

> Where ar2 and ar3 contain 0x04A4 and 0x04A5 (ie < 0x1fff and hence in dual
> access memory according to the TI manual). This instruction gives strange
> results (I tried 0+= 1*1 = FFFF7DDE ).

Are you saying that address 0x04A4 contained the value 0x0001, 0x04A5 the
value 0x0001, and accumulator A the value 0x00 0000 0000 before the MACSU,
then after the MACSU the accumulator was 00 FFFF 7DDE? If so, this makes no
sense.

Quote:> I have tried calling functions in the TI
> DSPLib (mul32) and this returned strange results as well. I have FRCT =1, SXM = 1
> and OVA = 0.

Just to see what happens, try the same thing with SXM = 0.

Quote:> The only thing I can think of is that the memory is not operating
> in dual access mode. Do I need to set up the DSP to enable the bottom 8K as dual
> access ram.

No, you shouldn't have to worry about that at all. The worst that could
happen is that you'd be charged an extra cycle.

Quote:> Does anyone have any other suggestions of why dual access operations
> would not work?

No. It looks fine to me. Just to see what happens, try putting the second
address (the "ymem") into 0x0CA4 or greater. This puts it in another
block (blocks are 2k on the 5410).
--
%  Randy Yates                  % "...the answer lies within your soul
%% DIGITAL SOUND LABS           %       'cause no one knows which side
%%% Digital Audio Sig. Proc.    %                   the coin will fall."

http://personal.lig.bellsouth.net/~yatesc

 
 
 

C5410 Dual access operands

Post by Randy Yate » Thu, 01 Mar 2001 21:38:30



> Hi, I'm having problems using dual memory access operands on my TI C5410 (using
> a TIGER 5410.

> I'm trying the following:

> MACSU *AR2, *AR3, A

> Where ar2 and ar3 contain 0x04A4 and 0x04A5 (ie < 0x1fff and hence in dual
> access memory according to the TI manual). This instruction gives strange
> results (I tried 0+= 1*1 = FFFF7DDE ). I have tried calling functions in the TI
> DSPLib (mul32) and this returned strange results as well. I have FRCT =1, SXM = 1
> and OVA = 0. The only thing I can think of is that the memory is not operating
> in dual access mode. Do I need to set up the DSP to enable the bottom 8K as dual
> access ram. Does anyone have any other suggestions of why dual access operations
> would not work?

Christian,

Here's a couple of other questions and things to look at:

1. What is the value of the C16 bit in ST1?
2. What is the value of the ASM bits in ST1?
3. Are you sure you're looking at data in data memory and
   not program memory at 0x04A4, 0x04A5?
4. What's the value of the T register after the instruction? It
   should be the value *AR2.
5. What are the values of the MP/MC*, OVLY, DROM, SST, and SMUL bits in the PMST?

Finally, if all this looks right, it could be that you have a bad part.

To be absolutely safe, I would try the instruction with the chip configured
as follows:

  OVM = 0
  SXM = 0
  C16 = 0
  FRCT = 0
  ASM = 0
  MP/MC* = 1
  OVLY = 0
  DROM = 0
  SMUL = 0
  SST = 0

Good luck.
--
%  Randy Yates                  % "...the answer lies within your soul
%% DIGITAL SOUND LABS           %       'cause no one knows which side
%%% Digital Audio Sig. Proc.    %                   the coin will fall."

http://personal.lig.bellsouth.net/~yatesc

 
 
 

1. Dual Access RAM vs Dual Port RAM

To all People,

Is the DARAM ( dual Access RAM ) and Single Access RAM (SARAM) defined in C54x
series by TI same as Single and Dual Port RAM?

Dual Port RAM is one in which  '2 different locations can be accessed in one
cycle by 2 DIFFERENT data buses' - this is my understanding.Is this right too?

thnx and regs,
g,s,v

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