Can any of you DEC people on the net answer the following 21064-AA Alpha
Questions? You can mail your replies or post them if I have my facts
wrong or you feel the need to continue this thread.
1) I read that the 21064 divide unit is not pipelined and takes one cycle
per bit to produce a result. Isn't this going to kill floating point
performance? FP constants can be converted by the compiler but
what about the rest of the divides? Doesn't the scoreboard have to stall
for 64 cycles to get the result of a divide with data depenencies? I'm
lead to think that DEC isn't interested in the FP performance of this chip,
or do I have my facts wrong?
2) The 21064 has no integer divide. Again, isn't this going to make math
performance poor. Integer constants can be converted to multiplies
but this is only a partial solution.
3) The manuals say that the 21064 is superpipelined. Where? How can this
claim be justified in light of the floating point divider not being
pipelined at all? It seems to me that all issues are superscalar but
that there is no superpipelining.
4) In one place I'm sure I read that all memory accesses are 64-bit yet
there are provisions for long word writes discussed elsewhere (in
multiprocesor environments, for example). Which is it?
Thanks in advance.
Keith R. Scidmore
P.S. I cancelled two earlier versions of this article that were mangled.
I hope it worked.