ASIC emulation (Quickturn, etc.)

ASIC emulation (Quickturn, etc.)

Post by Dan Lind » Thu, 01 Dec 1994 20:10:25



We're looking into ASIC emulation of the Quickturn variety and are
interested in experiences with Quickturn or any other FPGA-based emulation
systems.  Can you just drop a design on it and start running test vectors
through, or do you still have do some FPGA-like hardware design?  Does it
scale well to large emulations, say of a complete CPU or even multiple
chips?  We hear that the emulation runs 100 times slower than actual
hardware (which seems a little slow).  Are the FPGAs really that much
slower individually or is it a problem with their combination into a larger
system?

Any insights, experiences and/or references to articles describing
experiences would be greatly appreciated.  I will summarize responses for
the net.  Thanks again.

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ASIC emulation (Quickturn, etc.)

Post by Mike But » Fri, 02 Dec 1994 04:35:14



> We're looking into ASIC emulation of the Quickturn variety and are
> interested in experiences with Quickturn or any other FPGA-based emulation
> systems.  

> Can you just drop a design on it and start running test vectors
> through, or do you still have do some FPGA-like hardware design?

Yes you can.  All the FPGA-specific details are completely contained
within the design compiler, which does the technology mapping from the
source netlist and libraries into the FPGAs.  The emulation user sees
the design elements, netnames, etc. in the design's terms.  After running
your vectors, or even without vectors, you can go directly in-circuit.

Quote:> Does it scale well to large emulations, say of a complete CPU or even
> multiple chips?  

It scales very well to large emulations.  Intel, Sun, and many other
major developers are emulating entire CPU designs, at 2 million gates and more.
Quickturn's System Emulator M3000 has a 3 million gate capacity, with
provisions for multi-M3000 systems that allow over 10 million gate emulations
off the shelf.  Most CPU developers and many ASSP and ASIC projects now use
Quickturn emulators to run OSs and applications before tapeout.

Quote:> We hear that the emulation runs 100 times slower than actual hardware
> (which seems a little slow).  Are the FPGAs really that much slower
> individually or is it a problem with their combination into a larger system?

The programmable interconnect inside and between FPGAs does take more time
than real metal and wires, because of RC delays in pass transistors and many
more chip-crossings.  100X slowdown is an upper bound in our experience.  
Most emulations run from 1 to 8 MHz.  That's 3 to 5 orders of magnitude faster
than cycle-based simulators, which is the difference between running lots of
real code and just doing vectors or one OS boot.  Multi-million-gate CPU
emulations are slower than 200K gate ASIC emulations, but the CPU projects find
the speed is plenty for what they do so it all works out.  ASICs typically run
at multi-MHz in current-generation emulators, and there are many techniques
for successfully matching the target system's speed to the emulator.

Quote:> Any insights, experiences and/or references to articles describing
> experiences would be greatly appreciated.  I will summarize responses for
> the net.  Thanks again.

A detailed and quantitative article written by a user is called "Logic Design
Aids Design Process", by Jim Gateley of Sun, in the July 1994 issue of
ASIC & EDA.  It's an account of the MicroSPARC II project's experiences with
the Quickturn Enterprise (previous generation) logic emulator on a 200K
gate 32-bit SPARC CPU.

"During the 25 days prior to tapeout, the emulated processor and testbed
system successfully executed power-on self tests and open boot PROM, booted
single- and multi-user Solaris, Open Windows, and Open Windows applications.
Altogether, emulation logged 15 bugs and enhancements against MicroSPARC II,
PROM, and the kernel before tapeout. First silicon was very clean.  
MicroSPARC II shipped three months early."

           --Mike Butts, Emulation Architect,

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