Hennessy & Patterson Computer Architecture book: book-signing

Hennessy & Patterson Computer Architecture book: book-signing

Post by John Mash » Sat, 14 Apr 1990 11:06:10



Sorry there isn't a comp.arch.northern.california, but this is still
probably the best newsgroup for this:

The signing will be Computer Literacy (San Jose branch 2590 North 1st)
6:30--8:30 PM Thursday April 19.

So, if your copy is not autographed already, bring it and make these guys
write....
--
-john mashey    DISCLAIMER: <generic disclaimer, I speak for me only, etc>

DDD:    408-991-0253 or 408-720-1700, x253, or 408-524-7015
USPS:   MIPS Computer Systems, 930 E. Arques, Sunnyvale, CA 94086

 
 
 

1. Book availability: Hennessy/Patterson: Computer Architecture

Many of you have asked about the availability of

COMPUTER ARCHITECTURE:  A QUANTITATIVE APPROACH, by John Hennessy
(Stanford) and Dave Patterson (UC Berkeley).

This book is now available through technical bookstores, and should be
in-stock at the larger stores in major cities.  It can also be ordered
directly from the publisher:

Morgan Kaufmann Publishers,
2929 Campus Drive, Ste 260,
San Mateo, CA 94403,
Tel 415/965-4081.
VISA, Mastercard, personal checks and money orders will be accepted.
The cost of the title is $54.95 plus $3.50 shipping/handling for
each copy ordered.

Contents:

1. Fundamentals of Computer Design.
2. Performance & Cost.
3. Instruction Set Design:  Alternatives and Principles.
4. Instruction Set Examples and Measurements of Use.
5. Basic Processor Implementation Techniques.
6. Pipelining.
7. Vector Processors.
8. Memory Hierarchy Design.
9. Input/Output.
10. Future Directions & Parallel Computation.
Appendices:
A) Computer Arithmetic, by David Goldberg (Xerox PARC)
B) Complete Instruction Set Tables (VAX, 360, 8086)
C) Detailed Instruction Set Measurements (VAX, 360, 8086, DLX)
D) Time Versus Frequency Measurements
   (VAX 11/780, IBM 370/168, 8086 in an IBM PC, DLX)
E) Survey of RISC Architectures
   (DLX, i860, MIPS, M88000, SPARC).

Another title of interest that expands upon performance issues for
cache and memeory hierarchies is due to be published May 27th, also
from Morgan Kaufmann:

CACHE & MEMORY HIERARCHY DESIGN:  A PERFORMANCE DIRECTED APPROACH,
by Steven A. Przybylski (MIPS), $33.95
Contents:  Intro.  Background Material.  The Cache Design Problem
and its Solution.  Performance)Directed Cache Design.  Multi-Level
Cache Hierarchies.  Summary, Implications and Conclusions.
Appendices:  A) Validation of Empirical Results, B) Modeling Write
Strategy Effects.  
--


Please send responses to the author of the message, not the poster.

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