IC design/Poland

IC design/Poland

Post by Maciej S » Tue, 26 Jun 2001 20:40:46

Main Digital Silicon Project Leader involved in the digital IC design
competence growth from the start.

Project leader should have proven ability to lead teams of 8 or more people
through the full design lifecycle (from specification through to tape-out)
and design flow of a new IC development (i.e. not just re-spins).

The person should have worked with a number of different customers to gain
different perspectives of Silicon design.
They should be familiar with all the current CAD tools.
We expect that the minimum experience required to do this job would be 8
A personal history of significant achievement is required.
Ideally this experience would have been gained in telecommunications
application areas.

This job will involve the development of new engineering teams in an
exciting, high-growth environment.

In terms of personal characteristics, the person should:
- Be willing and able to train people
- Take responsibility
- Be a problem solver in the absence of full information

This person is required to work in Poland with a highly talented team of
engineers for pre*ly western european and US customers.

Please contact


1. US-CA Positions - Physcial IC Design Layout Engineer


This placement available notice is brought by Dino !

I am a recruiting independent and works for a close relation
with the candidate. For me the candidate is a person and not a
resume !!

information as indicated below:


Job code                : NAR-2102 when responding to this ad.
Job Title               :  Physcial IC Design Layout Engineer
Job Location    : CA - Los Angeles
Start Date              : earliest
Required Skills : This position requires a BS or MS with 2
years of experience with Cadence*, Avanti*, or Mentor Graphics*
tools and DRC, LVC, and RC extraction and verification
procedures. Understanding of electronic circuitry and the
utilized semiconductor technologies is a plus.

Responsibilities        : Work with circuit designers to translate and
lay out full-custom analog and mixed signal circuits in various
technologies including CMOS, SiGe, GaAs and InP FET, and bipolar

Resume Attached         : Yes
Your Day Phone  :
Your Work Phone :
Current Location        :
Relocation is okay      : Yes / No
Salary / Rate           :
Any other information   :

Best Wishes !
Dino Bareja
=========== FELLOWS INC. ===============


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