'030 burst mode (was Re: Mac IIci wait states)

'030 burst mode (was Re: Mac IIci wait states)

Post by Paul Jaco » Fri, 02 Nov 1990 04:05:00

>>Yes, both the data and instruction caches are enabled and burst enabled

during the boot process.
  So I assume that Jim Hamilton's "CacheControl" cdev just goes out to the
chip and resets the appropriate bit(s) to disable or re-enable the cache(s)?
  Another question: Are there any stats on how often the '030 Macs are able to
utilize burst mode?
| UUCP: {rosevax, crash, orator}!orbit!pnet51!pj |  Working with idiots keeps |


1. Mac IIci Wait states (was Re: Mac IIci benchmarks)

Sorry about that.

I was trying to keep the comparison between the IIcx and the IIci
simple -- perhaps too simple.

The bottom line is that the IIci takes an extra cycle for reads relative
to the IIcx (same as SE/30, IIx).

Noah:  Why does the IIci use synchronous access?  To improve the cache
performance perhaps?  What is the situation with a chache board installed?

The '030 user's manual says "The data burst enable bit must be set to
enable burst filling of the data cache."

Anyone know if this bit is set when running user code?

Larry Hutchinson, Tektronix, Inc. PO Box 500, MS 50-383, Beaverton, OR 97077
UUCP:   [uunet|ucbvax|decvax|hplabs]!tektronix!tekgvs!larryh

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