>>Noah Price of Apple confirmed my suspicions that the IIci is running two
>>wait states and that the SE/30 etc. runs one wait state.
>Actually, the IIci runs three wait states for random reads, since they're now
>synchronous which means a zero wait state random read would be 2 clocks.
I was trying to keep the comparison between the IIcx and the IIci
simple -- perhaps too simple.
The bottom line is that the IIci takes an extra cycle for reads relative
to the IIcx (same as SE/30, IIx).
Noah: Why does the IIci use synchronous access? To improve the cache
performance perhaps? What is the situation with a chache board installed?
The '030 user's manual says "The data burst enable bit must be set toQuote:>It's not quite that easy though, since the IIci does burst reads into the
>on-chip cache which are 5 clocks for the first longword access, followed three
>2 clock accesses for the other three long words in the burst.
enable burst filling of the data cache."
Anyone know if this bit is set when running user code?
Larry Hutchinson, Tektronix, Inc. PO Box 500, MS 50-383, Beaverton, OR 97077