How to flush instruction cache on MacBSD ?

How to flush instruction cache on MacBSD ?

Post by Satoshi Adac » Wed, 07 May 1997 04:00:00



Dear Developers of NetBSD,

I am now porting an interpreter/compiler system for the language ML (SML/NJ)
to NetBSD running over Macintosh PowerBook 550C (CPU=MC68040).

I found that the interpreter/compiler is very unstable when it is executed.
I am now doughting that this unstability may be resulted from the lack of the
functionality on MacBSD to flush the instruction cache according to
the request from a user process.

The object modules in ML are first loaded/generated as data into the system.
Then, they are regarded as programs later.

In order to keep the consistency among main memory/data cache and instruction
cache, the instruction cache have to be flushed explicitly at several points
in the runtime system of SML/NJ.

Actually, a header file "ml_os.h" in SML/NJ has the following fragment of
code:

-------------------------------------------------------------------------------
...
/* cache-flushing stuff */

#if defined(MIPS)
#ifdef sony_news
#include <machine/sysnews.h>
#    define FlushICache(addr, size)       \
        sysnews(NEWS_CACHEFLUSH, addr, size, FLUSH_ICACHE)
/* SYS_sysnews will be defined in syscall.h, in OS 4.1 */
#undef SYS_sysnews
#else
#ifndef MACH
#include <sys/sysmips.h>
#endif
#include <errno.h>
extern int errno;               /* some header files are missing this decl */
#  ifdef SGI
/* NOTE: need to flush both caches on R4000 machines, since the
 * primary data cache is write-back.
 */
#  include <sys/cachectl.h>
#  define  FlushICache(addr, size)      \
        (cacheflush((void *)(addr), size, BCACHE))
#  else
#    include <sys/syscall.h>
#    include <mips/cachectl.h>
#    ifdef MACH
#    define MIPS_CACHEFLUSH 0x104
#    endif
#    define FlushICache(addr, size)       \
        (syscall(SYS_sysmips, MIPS_CACHEFLUSH, (addr), (size), ICACHE, 0))
#  endif
#endif
#else
#ifdef NeXT
#  define FlushICache(addr, size)     asm ("trap #2")
#else
#ifdef RS6000
   extern FlushICache();
   extern iCacheLineSize();
#else
#ifdef SPARC
   extern FlushICache();
#else
#ifdef HPPA
#  define FlushICache(addr, size) flush_icache(addr, size)
#else
#ifdef THINK_C
#  define FlushICache(addr, size)     FlushCacheRange((void *)(addr), size)
#else
#  define FlushICache(addr, size)
#endif
#endif
#endif
#endif
#endif
#endif
...
-------------------------------------------------------------------------------

From this fragment, we know how the instruction cache can be fulshed for
many platforms.

I inspected carefully the kernel source code of NetBSD 1.2D for Mac68K
to search some system call to flush the instruction cache.
However, I could not find such a system call.

Maybe, NetBSD 1.2D (Mac68K) does not have such an interface to
flush the instruction cache according to the request from a user process.

If this is true, it seems to be a severe deficiency of NetBSD,
since the functionality to flush the instruction cache is necessary
not only for ML systems, but also Lisp systems and many other language systems
in which a generated module is first treated as data and becomes a program
later.

Furthermore, the functionality to flush the instruction cache is necessary
even for GNU C compiler to compile a nested function correctly.
(See the configuration file in GCC for NEXTSTEP (M68K).)

I wonder what I shall do...

Is there some project in NetBSD on its way to add the new system call
to flush the instruction cache ?

If there is no such project, is it OK for me to modify and extend
the existing souce code of NetBSD to support the system call for
flushing instruction cache ?
(After the modification, if SML/NJ system becomes stable, I may distribute
the modified source code of NetBSD and the patch for SML/NJ to Internet.)

In this case, what is the cleanest interface (system call) to flush
the instruction and/or data cache(s) ?

Do you have some suggestion ?

Thank you for your attention.
Any suggestions are really welcome.

Sincerely yours,

Satoshi Adachi

Department of Applied Physics,
Tokyo Institute of Technology

Oookayama 2-12-1, Meguro,
Tokyo 152, JAPAN

 
 
 

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