by Hi. I'm peeking at the src at 4.3BSD, especially at the code for
adjtime. The routine adjusts the system's clock (when given a number
of microseconds to differ). After it figures out how much has to
change, this is (summarized) what happens:
Call splclock
this copies the contents of processor register
$18 to r0 (the return value) and copies the value
$0x18 into this same register.
Do some math to figure out the remaining adjustment
Call splx with the return value from the splclock.
Now, register $18 is the Interval Count Control (according to the VAX
hardware handbook). The bit pattern from $0x18 sets the 2^3 bit.
But the manual claims that this bit MUST BE ZERO to work. The bit set
in the 2^4 position tells the machine to transfer the Next Interval
Count Register into the systems Interval Count Register.
So. That's what the code and the FM's say. But how does the time
actually change? I don't see a set of the Next Interval register.
What was there, and what effect does it have to load a seemingly
random register over the machine's system clock? And, where does the
computed change fit it? If the math is meant to be a delay loop, then
how can one slow the clock down?
Have I missed something here?? Any help would be appreciated!
j
--
Jeffrey L. Bromberger
System Operator---City College of New York---Science Computing Facility
Anywhere!{cmcl2,philabs,phri}!ccnysci!jeffrey