> |> Why not let make itself do the work, which does substitute previously
> |> defined vars? I.e. for the above
> |>
> |> if FLAG1
> |> FLAG1_SOURCES = c.c
> |> else
> |> FLAG1_SOURCES = d.c
> |> endif
> |> program_SOURCES = a.c b.c $(FLAG1_SOURCES)
> The problem lies in automake (or elsewhere). The .c-filenames in
> program_SOURCES are rewritten to .o-depencies, but that action seems
> to ignore any conditionally defined variables in the file
> list. Variables without conditions work... Then the resulting
> object list (*_OBJECTS) in the makefile simply misses the files in
> the variables. Of course I can put common files in variables and
> conditionnaly set the _SOURCES, but that still requires all
> combinations...
Conditionally compiling with automake is not perfect yet. I would
suggest that you do this:
EXTRA_program_SOURCES = file3a.c file3b.c file3c.c
You have to AC_SUBST(EXTRA_PROGRAM_FILES) in configure.ac, and define
what extra source files need compiling in this variable. This is not
too great, as it means that logic that should be in the Makefile goes
in configure.ac, making it overly complex. Last time I tried, I
couldn't use make macros in automake declarations e.g.:
program_SOURCES = file1.c file2.c $(EXTRA_PROGRAM_FILES)
I found a horrible hack to get around this.
EXTRA_program_SOURCES = file3a.c file3b.c file3c.c
in configure.ac:
if ... ; then
EXTRA_PROGRAM_FILES="\$(EXTRA_program_SOURCES)"
fi
However, this is dependent on the order of definitions in the
Makefile, and is again overly complex, but does move some logic out of
configure.ac.
Automake 1.5 is now out. I have not tried it yet, but it is possible
these issues have been fixed. They are only due to automake being too
picky when parsing Makefile.am, although I'm sure there were valid
reasons for making it so.
Regards,
Roger
--
Roger Leigh ** Registration Number: 151826, http://counter.li.org **
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