Mapping IO device to Cacheable memory

Mapping IO device to Cacheable memory

Post by Eca » Sat, 01 Aug 1998 04:00:00



Hello,
 I am trying to map an IO peripheral device to _Cacheable_ memory, to
improve performance of read/write accesses to it. Is there a kernel
routine to do so? vremap()? Normally IO devices are mapped as uncacheable.
Is this specified as default anywhere in the kernel or special registers?
  This is on Pentium Pro, with Memory Type Range Registers (MTRRs)
enabled. Will I need to modify MTRR group of registers explicity (using
RDMSR/WRMSR instructions) to mark the mapped region as Cacheable?

Thanks for any responses,
Ecap


 
 
 

Mapping IO device to Cacheable memory

Post by Sascha Bohnenkam » Sat, 01 Aug 1998 04:00:00


Quote:>Hello,
> I am trying to map an IO peripheral device to _Cacheable_ memory, to
>improve performance of read/write accesses to it. Is there a kernel
>routine to do so? vremap()? Normally IO devices are mapped as uncacheable.
>Is this specified as default anywhere in the kernel or special registers?
>  This is on Pentium Pro, with Memory Type Range Registers (MTRRs)
>enabled. Will I need to modify MTRR group of registers explicity (using
>RDMSR/WRMSR instructions) to mark the mapped region as Cacheable?

it is IMHO not possible without loosing control, because the state of the
io-registers could change without your cpu seeing it ... because the cache
contains other values

 
 
 

1. Memory mapped IO for an ISA device

I have an ISA network card that can use a 4 KB memory-mapped address
space for communication.  It's a PnP card and it can locate the base
address for this window anywhere within an (aligned) 24 bit address
space.  My question is: where should it *actually* locate this address
space so that Linux reserves this spaces for the device, not system RAM?

Now I know that Linux maps bus address space into a high memory area,
and an ISA device driver must use ioremap to translate base addresses
into offsets into kernel memory.  But I don't know how this memory is
reserved in the first place.  How does the memory address translation
hardware become aware that a particular range of physical addresses is
assigned to an ISA device, not system RAM?  How does Linux ensure that a
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