Getting the fault adress in page faults.

Getting the fault adress in page faults.

Post by Andreas Kostyrka ( yac » Mon, 06 Mar 1995 08:01:12



Hi,

 I just wanted to ask, if there is a way in linux to get
the offending adress in a SIGSEGV-handler?
(Need that for a port. At least SunOS, OSF/1 and Ultrix support that feature.)

thx in advance,

Andreas Kostyrka

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Getting the fault adress in page faults.

Post by Martin v. Loew » Tue, 07 Mar 1995 19:36:59




Quote:> I just wanted to ask, if there is a way in linux to get
>the offending adress in a SIGSEGV-handler?
>(Need that for a port. At least SunOS, OSF/1 and Ultrix support that feature.)

>thx in advance,

From the sigcontext (as passed to the signal handler), take the eip register
(and maybe the cs register) to get the faulting instruction. Look at
the sources of Wine or dosemu for a sample code.

Enjoy,
Martin

 
 
 

Getting the fault adress in page faults.

Post by Bruno Haib » Thu, 09 Mar 1995 23:52:08


Quote:>> I just wanted to ask, if there is a way in linux to get
>> the offending adress in a SIGSEGV-handler?

> From the sigcontext (as passed to the signal handler),

Yes. Declare your handler like this:

  #include <asm/signal.h>
  void sigsegv_handler(int sig, struct sigcontext_struct context)
  {...}

Quote:> take the eip register
> (and maybe the cs register) to get the faulting instruction. Look at
> the sources of Wine or dosemu for a sample code.

No. If you are starting with the EIP register you need a disassembler
in your source.

You get the fault address for free in the context.cr2 field.
(Unless the fault address is >= 0xC0000000, but in that case it is better
to dump core anyway.)

                    Bruno Haible

 
 
 

1. Page Faults/Segmentation Faults??

Many postings on this group have suggested that what you are seeing is
the result of a problem with the CPU's external cache. Try disabling
external cache in your BIOS setup.

I had very similar problems that were solved with this method. Of
course, there's a significant performance hit in not using a L2 cache.

Perry

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