> I have a few points of confusion, and I would deeply appreciate any
> clarifications. They concern the three primary structures task_struct,
> thread_struct, and tss_struct. (in kernel 2.4.x)
thread_struct contains architecture dependant process information.
tss_struct is x86-specific, defined by the hardware.
The TSS (Task State Segment) structure is defined by the processor forQuote:> 1) I am having a difficult time understanding how tss_struct could be moved
> out of task_struct (per process basis, as one would expect) to a statically
> allocated array (per CPU basis, ???). How can these registers be saved
> across context switches, when there are only as many such structures as
> there are CPUs? I did not follow the explanation in UTLK.
hardware task switching. Earlier versions of Linux on the x86 used one
TSS for each process and used hardware task switching. This effectively
limited the number of processes to about 500. We now have one TSS per
cpu, and do software task switching.
The x86 architecture has 4 priviledge levels (aka rings), with LinuxQuote:> 2) Why the multiple stack pointers and stack segments in tss_struct?
only using ring 3 (user) and ring 0 (kernel). When moving to a higher
privilege level (smaller numerically), a new stack pointer is loaded
fron the corresponding pointer in the TSS.
The kernel stack pointer for the current process. This is copied intoQuote:> 3) What is esp0 in thread_struct?
tss->esp0 when the process becomes current on a cpu.
Segment registers are only 16 bits. the __*h values are the high 16Quote:> 4) What are the members suffixed with 'h' in tss_struct? I thought they were
> the segment shadow registers until I saw the member __ldth, because I didn't
> believe that ldt had a shadow register.
bits that are filler.
To avoid any namespace collisions.Quote:> 5) Is there a particular reason for the double underscore convention
> prefixing certain members?
I suggest that you read the Intel documentation:
In particular Chapter 6 Task Management
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