I'm a bit curious my self, in theory the IO_APIC should drastically
reduce interrupt latency. An x86 has two interrupt pins, IRQ and NMI.
The first 8259 are (if remember correctly) connected to the IRQ only,
and the second is connected to IRQ2 on the first 8259 (cascade).
When an Int is triggered the CPU has to go out and read the registers in
the two 8259's to find the triggered interrupt, and call the
corresponding int handler. THe thing is that the 8259 of today are
located in the south bridge, and there are an internal ISA bus in the
south bridge, but still running at the amazing speed in 10MHz.
THe IO-APIC, when used, the CPU is set to use the two IRQ pins (IRQ, and
NMI) as a two bit bus, and the IO_APIC send the interruot vector on this
bus, saving the CPU from reading the vector over the slow ISA bus, and
can call the interrupt directly.
However, I've on a couple of occations tried to measure the interrupt
latency and I end up with that the latency is the same either I use 8259
or APIC. Most likely a problem with my measuring. Especially since you
see better thruput using APIC. However I would like to see you get the
same results with a different NIC.
Now, if our UDP packetloss are due to bursts, and not sustained traffic,
and you have a NIC that uses memory descriptors (like Intel eepro100
chips, or 3com 90x, most new chips do), you can do a workaround by
increasing the receive ring size in the driver.
> I already asked this question but did not get any responses. Please
> condider answering.
> Using the old i8259 interrupts controller, my 1-way Linux2.4.16 box
> livelocks when receiving a high rate UDP flow (interrupt rate is so
> high that the NET_RX_SOFTIRQ never gets the chance to pull the
> packets off the backlog queue). However, the receive livelock
> phenomenom completely disappears when making use of the IO-APIC.
> Does anyone have an explanation for this?
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