Very Computer

Here goes pre10.

This version fixes the NFS hang which was introduced in early 2.4.20-pre's
plus some smaller fixes.

Summary of changes from v2.4.20-pre9 to v2.4.20-pre10
============================================

  o net/8021q/vlan_dev.c: Fix lockup when setting egress priority

  o net/sched/sch_htb.c: Check that node is really leaf before modifying cl->un.leaf

  o remove a dead extern
  o fix some O_DIRECT read cornercases

  o Changed EXTRAVERSION to pre10

  o Several S390 3270 fixes

  o [IPV4/IPV6]: General cleanups

  o Configure.help entries for BeFS
  o trivial Configure.help bits from -ac

  o Fusion driver fixes

  o IEEE1394 updates

  o PPC32: Tweak the way various PPC cpus (750FX, 750CX, 745x) are set up
  o PPC32: Better support for the 750FX and 7455 PPC cpus
  o PPC32: support for new powermacs including the Xserve and eMac
  o PPC32: idle loop improvements for PPC 6xx/7xx/7xxx processors
  o PPC32: PCI fix for PCI-PCI bridges with the I/O window closed
  o PPC32: Fix race in i2c-keywest
  o PPC32: ide-pmac update
  o PPC32: ADB core locking fix
  o PPC32: Update net driver config description

  o JFS: Releasing LOGGC_LOCK too early

  o [VLAN]: Accept zero vlan at unregister
  o net/core/dev.c: Print lethal dev/protocol errors with KERN_CRIT
  o net/8021q/vlan.c: Unsigned value may never be < 0

  o JFFS2 updates

  o Fix speed braindamage of mass exit of thread groups

  o [NET]: Remove net_call_rx_atomic
  o [BRIDGE]: Skip the LISTENING_STP state if STP is disabled
  o [BRIDGE]: take BR_NETPROTO_LOCK for unlinking bridge device slaves

  o PPC32: Make the heartbeat count and reset variables be per-cpu
  o PPC32: update the default configs in arch/ppc/configs
  o PPC32: define register numbers for extra BATs; patch from Cort Dougan
  o PPC32: define TIOCM_MODEM_BITS, irda wants it
  o PPC32: Add support for the Total Impact BRIQ platform

  o get_pid() typo fix

  o Workaround NFS hangs introduced in 2.4.20-pre

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--

[ 2.4.20-pre10-brlvger.patch < 1K ]
--- linux/drivers/usb/brlvger.c.orig    Thu Aug 29 10:30:50 2002

     ({ printk(KERN_ERR "Voyager: " args); \
        printk("\n"); })
 #define dbgprint(fmt, args...) \
-    ({ printk(KERN_DEBUG "Voyager: %s: " fmt, __FUNCTION__, ##args); \
+    ({ printk(KERN_DEBUG "Voyager: %s: " fmt, __FUNCTION__ , ##args); \
        printk("\n"); })
 #define dbg(args...) \
     ({ if(debug >= 1) dbgprint(args); })

| Here goes pre10.

When will the PDC20268 driver go with UDMA 100 in your tree?
Before or after 2.4.20?

Uniform Multi-Platform E-IDE driver Revision: 6.31
ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx
ICH2: IDE controller on PCI bus 00 dev f9
ICH2: chipset revision 2
ICH2: not 100% native mode: will probe irqs later
    ide0: BM-DMA at 0x9800-0x9807, BIOS settings: hda:DMA, hdb:pio
    ide1: BM-DMA at 0x9808-0x980f, BIOS settings: hdc:DMA, hdd:pio
PDC20268: IDE controller on PCI bus 02 dev 68
PCI: Found IRQ 9 for device 02:0d.0
PCI: Sharing IRQ 9 with 02:09.0
PDC20268: chipset revision 1
PDC20268: not 100% native mode: will probe irqs later
PDC20268: (U)DMA Burst Bit ENABLED Primary MASTER Mode
Secondary MASTER Mode.
    ide2: BM-DMA at 0xa400-0xa407, BIOS settings: hde:pio, hdf:pio
    ide3: BM-DMA at 0xa408-0xa40f, BIOS settings: hdg:pio, hdh:pio
hda: IC35L060AVVA07-0, ATA DISK drive
hdc: IC35L060AVVA07-0, ATA DISK drive
hde: IC35L060AVVA07-0, ATA DISK drive
hdg: IC35L060AVVA07-0, ATA DISK drive
ide0 at 0x1f0-0x1f7,0x3f6 on irq 14
ide1 at 0x170-0x177,0x376 on irq 15
ide2 at 0xb800-0xb807,0xb402 on irq 9
ide3 at 0xb000-0xb007,0xa802 on irq 9
blk: queue c034d544, I/O limit 4095Mb (mask 0xffffffff)
hda: 120103200 sectors (61493 MB) w/1863KiB Cache, CHS=7476/255/63, UDMA(100)
blk: queue c034d8a8, I/O limit 4095Mb (mask 0xffffffff)
hdc: 120103200 sectors (61493 MB) w/1863KiB Cache, CHS=119150/16/63, UDMA(100)
blk: queue c034dc0c, I/O limit 4095Mb (mask 0xffffffff)
hde: 120103200 sectors (61493 MB) w/1863KiB Cache, CHS=119150/16/63, UDMA(33)
blk: queue c034df70, I/O limit 4095Mb (mask 0xffffffff)
hdg: 120103200 sectors (61493 MB) w/1863KiB Cache, CHS=119150/16/63, UDMA(33)

Weird CHS on hda is due bogus BIOS?

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PDC20268: IDE controller on PCI bus 00 dev 98
PDC20268: chipset revision 1
PDC20268: not 100% native mode: will probe irqs later
PDC20268: (U)DMA Burst Bit DISABLED Primary PCI Mode Secondary PCI Mode.
    ide2: BM-DMA at 0xfce0-0xfce7, BIOS settings: hde:pio, hdf:pio
    ide3: BM-DMA at 0xfce8-0xfcef, BIOS settings: hdg:pio, hdh:pio
hde: Maxtor 4D080H4, ATA DISK drive
hdg: Maxtor 4G120J6, ATA DISK drive
ide2 at 0xfcc8-0xfccf,0xfcda on irq 10
ide3 at 0xfcd0-0xfcd7,0xfcde on irq 10
hde: 160086528 sectors (81964 MB) w/2048KiB Cache, CHS=9964/255/63, UDMA(100)
hdg: 240121728 sectors (122942 MB) w/2048KiB Cache, CHS=14946/255/63, UDMA(100)

So there *is* UDMA 100 support...

Cheers,
Juri

--

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|> hde: 120103200 sectors (61493 MB) w/1863KiB Cache, CHS=119150/16/63, UDMA(33)
|> hdg: 120103200 sectors (61493 MB) w/1863KiB Cache, CHS=119150/16/63, UDMA(33)

| hde: 160086528 sectors (81964 MB) w/2048KiB Cache, CHS=9964/255/63, UDMA(100)
| hdg: 240121728 sectors (122942 MB) w/2048KiB Cache, CHS=14946/255/63, UDMA(100)
|
| So there *is* UDMA 100 support...

Yes, there was, but disabled during 2.4.20-pre. But why?

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