by Chang Q. » Thu, 02 May 1996 04:00:00
Hi
I have question related to makefile. I want to make a object that the source
Such as:
$(OBJS):$(SRCS)
$(CC) $<
where $(OBJS) and $(SRCS) are in different directory and both of them are
contained more than one file.
Thanks a lot!
1. makefile when SRC dir and OBJ dir differs?
Suffix rules only work when target and prerequisite are
in the same directory. But sometimes you want the object
files to be generated in some other directory since
directory gets messy and it makes you hard to see the
list of source files.
What may be a good solution to this ?
Is there any way doing this with suffix rules ?
Any good ideas / sugestoins are welcomed.
Thanks.
3. MAKE question.... different src and obj directories
5. cvs commit: src/include pthread_np.h src/lib/libc_r/uthread Makefile.inc uthread_main_np.c
6. Sysadmins - who's written this already?
7. diff -rcN ups-2.45.2/Makefile ups/Makefile
8. Retrieve files after tar -rf /dev/ftape
9. Release 5.0 (root@hollin.btc.adaptec.com:/
10. Does kbuild 2.5 support separate obj/src trees
13. automated diff'ing of src distributions