A basic Makefile question

A basic Makefile question

Post by Suzanne Bak » Wed, 02 Jul 2003 17:16:02



Hi,

I have read through the GNU Make website on the internet, but I am
still unsure of how to create the Makefile for multiple .c files(150
.c files to be exact)

The following is my Makefile for a 3 .c files and one .h file into one
single .exe file:
CFLAGS=

TGT=tt

OBJ=file1.o file2.o file3.o

$(TGT): $(OBJ)
       cc $(CFLAGS) $(OBJ) -o $(TGT);

file1.o: file1.c testheader.h
       cc -c file1.c;

file2.o: file2.c
       cc -c file2.c;

file3.o: file3.c testheader.h
       cc -c file3.c;

clean:
       rm -f *.o;

The above Makefile is for 3 .c files only. If I want to compile a
total of 150 different .c files, what should I do? Do I really have to
type out the following part for every single .c file?

file1.o: file1.c testheader.h
       cc -c file1.c;

I would greatly appreciate it if anyone can tell me a shorter and more
efficient method of compiling and linking all the 150 .c files into
one single .exe file.
Thanks alot in advance for your kind help.

Regards,
Suzanne

 
 
 

A basic Makefile question

Post by Eric » Wed, 02 Jul 2003 17:41:51




Quote:>I would greatly appreciate it if anyone can tell me a shorter and more
>efficient method of compiling and linking all the 150 .c files into
>one single .exe file.

Hi Suzanne,

The following is a makefile that you might find useful. It has
overhead in that it computes the dependencies at build time using a
few smart tricks. All you have to do is replace the name of the
executable, flags, and libs on the first 3 lines. Place the makefile
in the same directory as your source code and you should be in
business.

I got this makefile from a friend a while back so I'm not sure where
it is from. It was originally for .cpp files but I have replaced
g++/.cpp with gcc/.c in the makefile below (hope it still works!).

Hope it helps,
Eric.

---
EXECUTABLE = program
CPPFLAGS = -ggdb3 -Wall
LIBS = -lpthread
#################################################
CC = gcc
SRCS := $(wildcard *.c)
OBJS := $(patsubst %.c,%.o,$(SRCS))
DEPS := $(patsubst %.c,%.d,$(SRCS))
#################################################
all:    $(EXECUTABLE)

$(EXECUTABLE): $(DEPS) $(OBJS)
        $(CC) -o $(EXECUTABLE) $(OBJS) $(LIBS)

%.d: %.cpp


%.d: %.h


clean:
        -rm $(OBJS) $(EXECUTABLE) $(DEPS) *~

explain:





depends: $(DEPS)

-include $(DEPS)

run:    all
        ./$(EXECUTABLE)

debug:  all
        gdb $(EXECUTABLE)

clean-emacs:
        rm *~
---

 
 
 

A basic Makefile question

Post by M?ns Rullg? » Wed, 02 Jul 2003 17:34:21



> I have read through the GNU Make website on the internet, but I am
> still unsure of how to create the Makefile for multiple .c files(150
> .c files to be exact)

> The following is my Makefile for a 3 .c files and one .h file into one
> single .exe file:

[example makefile]

Quote:> The above Makefile is for 3 .c files only. If I want to compile a
> total of 150 different .c files, what should I do? Do I really have to
> type out the following part for every single .c file?

Not at all.  In fact, you don't need to write anything at all.  The
builtin rules of make will take care of that.  If you want dependency
tracking, you can put something like this at the end of your makefile.

----CUT----
depend: .depend

.depend: $(OBJ:.o=.c)

.PHONY: depend

include .depend
----CUT----

Then you just run "make depend" to update the dependencies on header
files.

--
M?ns Rullg?rd

 
 
 

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