Does full-speed 256 L2 cache reduce SMP efficiency?

Does full-speed 256 L2 cache reduce SMP efficiency?

Post by Steve Snyde » Wed, 16 Feb 2000 04:00:00

I have read that a full-speed 256KB L2 cache reduces SMP efficiency
relative to a half-speed 512KB cache.  For example, a P3/600e vs. a

Is this true?  Is there greater benefit in SMP to a larger L2 cache,
even if it is half as fast?

Thank you.

***** Steve Snyder *****


1. Q: Shared L2 cache on SMP system

I've purchased recently this specific motherboard (Tomcat IV Dual) with
2 P200/MMX, they're worth 398 BogoMips each (that's 796 BogoMips all
together !). But I don't know if this figure means anything at all.

Otherwise, the performance is not too bad at all.. :) Be a little more
specific about what you'd like to know about it.


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