I am considering building a system based on the Tyan S1832DL motherboard
which is based on the new BX chioset and supports dual processors.
Has anyone used this mb with Linux? How well does the mb perform? Any
problems, comments, suggestions.
I suggest you avoid the S1832DL!
I was all set to build a Linux system based on the S1832DL for myself, but
luckily I read a message on the linux-smp mailing list the very morning I
was going to purchase one. According to that message by Don Holmgren of
Fermilab, the S1832DL performs very poorly on the STREAM benchmark,
achieving approximately *half* the memory bandwidth of other single and
dual BX motherboards (around 135MB/sec versus 270MB/sec). This poor
performance has been confirmed by two additional individuals, both using
high quality memory that was also shown to perform properly in other
Enclosed below is the reply I sent to linux-smp after some investigation.
I also sent this information to Tyan Technical Support on June 14th, but as
of this writing (June 20th), I have received no response from Tyan.
I was all set to purchase one of these for my own use when I saw your message.
Larry Augustin of VA Research confirmed your numbers, and also ran a program I
wrote to dump the 440BX chipset registers on the Tyan S1832DL, Intel SE440BX,
and Intel N440BX motherboards. It looks to me like the setting of Bit 2 in the
NBXCFG register is the most likely reason for the memory bandwidth performance
degradation of the S1832DL relative to the SE440BX and N440BX. Quoting from
pages 42-43 of the 440BX chipset specification:
NBXCFG (NBX Configuration Register) [registers 53..50]
In-Order Queue Depth (IOQD) (RO). This bit reflects the value sampled on
A7# on the deassertion of the CPURST#. It indicates the depth of the
Pentium? Pro processor bus in-order queue (i.e., level of Pentium Pro
processor bus pipelining).
1 = In-order queue = maximum. If A7# is sampled "1" (i.e,. undriven on the
Pentium Pro processor bus), the depth of the Pentium Pro processor bus
in-order queue is configured to the maximum allowed by the Pentium Pro
processor protocol (i.e., 8). However, the actual maximum supported by the
82443BX is 4, and it is controlled by the 82443BX's Pentium Pro processor
interface logic using the BNR# signaling mechanism.
0 = A7# is sampled asserted (i.e., "0"). The depth of the Pentium Pro
processor bus in-order queue is set to 1 (i.e., no pipelining support on
the Pentium Pro processor bus).
NOTE: During reset, A7# can be driven either by the 82443BX or by an
external source as defined by the strapping option on the MAB11# pin.
The values from registers 53..50 on these three motherboards are:
S1832DL: 00000408 (Bit 2 OFF)
SE440BX: CF000004 (Bit 2 ON)
N440BX: 3F00018C (Bit 2 ON)
This indicates that Pentium Pro processor bus pipelining is disabled on the
S1832DL, but set to maximum on the SE440BX and N440BX. Unfortunately, this bit
is not writable so confirming this hypothesis is not a simple matter of writing
the correct value to PCI Configuration Space.