data & instruction cache size upgrade for PI?

data & instruction cache size upgrade for PI?

Post by Steve Rik » Wed, 03 Mar 1993 00:04:04



We have several 4D/20tg PIs, with differing data and instruction
cache sizes.

The largest have 32K data and 64K instruction, and these are still
quite useable machines for student work.

The smallest have 8K data and 16K instruction, and the lag-time
on the graphical login typeahead is almost unbearable.  I'll not
even mention how bad they perform otherwise.

My question is, what is involved in upgrading the data and instruction
cache sizes of these machines?  Is it a full CPU-board-type swap?  Can
it even be done?  $$??

Tnx in advance.

cheers,
sr.
--
|| Steve Rikli             |||  Visualization Lab               ||

|| 409-845-3465            |||  College Station, TX  77843-3137 ||

 
 
 

data & instruction cache size upgrade for PI?

Post by Steve Rik » Wed, 03 Mar 1993 16:03:05




>| We have several 4D/20tg PIs, with differing data and instruction
>| cache sizes.
>|
>| The largest have 32K data and 64K instruction, and these are still
>| quite useable machines for student work.
>|
>| The smallest have 8K data and 16K instruction, and the lag-time
>| on the graphical login typeahead is almost unbearable.  I'll not
>| even mention how bad they perform otherwise.
>|
>| My question is, what is involved in upgrading the data and instruction
>| cache sizes of these machines?  Is it a full CPU-board-type swap?  Can
>| it even be done?  $$??

>It seems more likely that the 32+64 systems are 4D/25's with
>a 20 MHz clock instead of the 12 MHz clock on the 20.  A relatively
>small number of 4D/20's at the very end of their life were built
>using the 25 CPU board at the lower clock rate, and hence have
>a larger cache, but the performance difference of the cache
>alone really wasn't all that great.

>Look at the hinv output and see what it says about CPU speed.

All of the 32/64K systems list their processor as 12MHz IP6--4d/20, right?
Is it possible that hinv is lying to me on the suspect systems?  Our sales
droid at the time sold them as 4d/20s--I'd be considerably surprised if it
were to turn out they're actually 4d/25s and we got more computer than we
paid for.  ;-)

I've gotten *numerous* responses telling me to check the main memory size
(32MB on all the above systems) because that's the slowdown problem.  But
I *know* it's not because they're *all* at 32MB regardless of the cache
size, but there's a noticeable difference between the machines' performance.

It would seem that I've gotten 3 of the 'relatively small number' of 4d/20s
with the 12MHz r3000 and the bigger caches.

Now, if the main memory size is the same on both of the machines in question,
and the performance difference in the cache size isn't all that great, what
else could be contributing to the exceptionally slow graphical startup/login
on the machines with the smaller cache?  Swap is the same, they're all
running 4.0.5a; I'm at a loss.  Could the chip revisions or graphics
revisions play a significant role here?

Quote:>There are no 20 to 25 upgrades available anydore, as far as I know,
>but upgrades to the 4D/35 (36 MHz R300A, 64+64 cache) are probably
>still available.

A kindly SGI fellow sent me the part number for a refurbished 4d/25 upgrade:
HUR-4D25A.  I can't speak for the availability, but I understand it lists
for $3500.  The 4d/35 upgrade Dave mentions goes for $9000 list, I believe.

cheers,
sr.
--
|| Steve Rikli             |||  Visualization Lab               ||

|| 409-845-3465            |||  College Station, TX  77843-3137 ||

 
 
 

data & instruction cache size upgrade for PI?

Post by Dave Ols » Wed, 03 Mar 1993 17:39:34



| Now, if the main memory size is the same on both of the machines in question,
| and the performance difference in the cache size isn't all that great, what
| else could be contributing to the exceptionally slow graphical startup/login
| on the machines with the smaller cache?  Swap is the same, they're all
| running 4.0.5a; I'm at a loss.  Could the chip revisions or graphics
| revisions play a significant role here?

Are some of them GR 1.1 graphics, and some 1.2?  Other than
different system disks, that's the only other think I can
think of, offhand.

| A kindly SGI fellow sent me the part number for a refurbished 4d/25 upgrade:
| HUR-4D25A.  I can't speak for the availability, but I understand it lists
| for $3500.  The 4d/35 upgrade Dave mentions goes for $9000 list, I believe.

Amazing.  We must have had a lot more 4D/25 CPU boards
come back as part of the 4D/35 upgrade than I realized.
I thought they would have all been long gone.
--
Let no one tell me that silence gives consent,  |   Dave Olson
because whoever is silent dissents.             |   Silicon Graphics, Inc.

 
 
 

data & instruction cache size upgrade for PI?

Post by Dave Ols » Wed, 03 Mar 1993 14:50:19



| We have several 4D/20tg PIs, with differing data and instruction
| cache sizes.
|
| The largest have 32K data and 64K instruction, and these are still
| quite useable machines for student work.
|
| The smallest have 8K data and 16K instruction, and the lag-time
| on the graphical login typeahead is almost unbearable.  I'll not
| even mention how bad they perform otherwise.
|
| My question is, what is involved in upgrading the data and instruction
| cache sizes of these machines?  Is it a full CPU-board-type swap?  Can
| it even be done?  $$??

It seems more likely that the 32+64 systems are 4D/25's with
a 20 MHz clock instead of the 12 MHz clock on the 20.  A relatively
small number of 4D/20's at the very end of their life were built
using the 25 CPU board at the lower clock rate, and hence have
a larger cache, but the performance difference of the cache
alone really wasn't all that great.

Look at the hinv output and see what it says about CPU speed.

There are no 20 to 25 upgrades available anydore, as far as I know,
but upgrades to the 4D/35 (36 MHz R300A, 64+64 cache) are probably
still available.
--
Let no one tell me that silence gives consent,  |   Dave Olson
because whoever is silent dissents.             |   Silicon Graphics, Inc.

 
 
 

data & instruction cache size upgrade for PI?

Post by R. Lamber » Thu, 04 Mar 1993 02:51:07


On a slightly different track: it looks like the R3k Indigo board
has only half of the possible number of cache chips installed.
At least the revision of the main board I have has some spare
'slots' which look like they were designed to take another bunch
of R3k cache chips (the Hitachi stuff).

Is it possible to expand the cache size by simply soldering in
a few of these chips? Yeah, I know these smd devices are
difficult to handle. Would be fun, though :-).

- Reinoud

 
 
 

data & instruction cache size upgrade for PI?

Post by Steve Rik » Thu, 04 Mar 1993 01:04:31




>| Now, if the main memory size is the same on both of the machines in question,
>| and the performance difference in the cache size isn't all that great, what
>| else could be contributing to the exceptionally slow graphical startup/login
>| on the machines with the smaller cache?  Swap is the same, they're all
>| running 4.0.5a; I'm at a loss.  Could the chip revisions or graphics
>| revisions play a significant role here?

>Are some of them GR 1.1 graphics, and some 1.2?  Other than
>different system disks, that's the only other think I can
>think of, offhand.

That's exactly the case.  If that might be the 'problem', then this
obviously begs the question:  "how do I go about upgrading the GR, if
that's possible".  [*danger* *danger*, new thread alert!!  ;-)  ]
I suspect the answer is probably the same, however.

Quote:>| A kindly SGI fellow sent me the part number for a refurbished 4d/25 upgrade:
>| HUR-4D25A.  I can't speak for the availability, but I understand it lists
>| for $3500.  The 4d/35 upgrade Dave mentions goes for $9000 list, I believe.

>Amazing.  We must have had a lot more 4D/25 CPU boards
>come back as part of the 4D/35 upgrade than I realized.
>I thought they would have all been long gone.

Well, you could be quite right (as usual), it may be that they all _are_
long gone.  I've not gone to the effort to investigate thoroughly.

cheers,
sr.
--
|| Steve Rikli             |||  Visualization Lab               ||

|| 409-845-3465            |||  College Station, TX  77843-3137 ||

 
 
 

data & instruction cache size upgrade for PI?

Post by Dave Ols » Thu, 04 Mar 1993 14:41:19



| >Are some of them GR 1.1 graphics, and some 1.2?  Other than
| >different system disks, that's the only other think I can
| >think of, offhand.
|
| That's exactly the case.  If that might be the 'problem', then this
| obviously begs the question:  "how do I go about upgrading the GR, if
| that's possible".  [*danger* *danger*, new thread alert!!  ;-)  ]
| I suspect the answer is probably the same, however.

Upgrades to gr1.2 are a single chip change (the raster engine chip).
It has better support for some common X operations.

At the time 401 released, they were available as a $100 US upgrade
(customer installable).  Last I heard (a couple of months ago),
they were still available from SGI Express.
--
Let no one tell me that silence gives consent,  |   Dave Olson
because whoever is silent dissents.             |   Silicon Graphics, Inc.

 
 
 

data & instruction cache size upgrade for PI?

Post by Dave Ols » Thu, 04 Mar 1993 14:42:11



| On a slightly different track: it looks like the R3k Indigo board
| has only half of the possible number of cache chips installed.
| At least the revision of the main board I have has some spare
| 'slots' which look like they were designed to take another bunch
| of R3k cache chips (the Hitachi stuff).

Those are not for cache chips, those are for some chips we used
during bring up and mfgr that allowed us to capture some more
information about the machine state on crashes.

Some systems even shipped with those chips installed, early on.
--
Let no one tell me that silence gives consent,  |   Dave Olson
because whoever is silent dissents.             |   Silicon Graphics, Inc.

 
 
 

data & instruction cache size upgrade for PI?

Post by Stan Jens » Fri, 05 Mar 1993 09:42:45



|> | >Are some of them GR 1.1 graphics, and some 1.2?  Other than
|> | >different system disks, that's the only other think I can
|> | >think of, offhand.
|> |
|> | That's exactly the case.  If that might be the 'problem', then this
|> | obviously begs the question:  "how do I go about upgrading the GR, if
|> | that's possible".  [*danger* *danger*, new thread alert!!  ;-)  ]
|> | I suspect the answer is probably the same, however.
|>
|> Upgrades to gr1.2 are a single chip change (the raster engine chip).
|> It has better support for some common X operations.
|>
|> At the time 401 released, they were available as a $100 US upgrade
|> (customer installable).  Last I heard (a couple of months ago),
|> they were still available from SGI Express.

Dave's right again! You can order the HUR-RE2 from SGI Express for $100 (list).
Our Remarketed Systems group has those, plus HUR-4D25A (4D/20 -> 4D/25),
HUR-4D35A (4D/25 -> 4D/35) & HUR-4D35B (4D/20 -> 4D/35), in stock on 3/1/93.
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1. Secondary unified instruction/data cache size

I have the following INDY machine:

Iris Audio Processor: version A2 revision 4.1.0
1 150 MHZ IP22 Processor
FPU: MIPS R4010 Floating Point Chip Revision: 0.0
CPU: MIPS R4400 Processor Chip Revision: 5.0
On-board serial ports: 2
On-board bi-directional parallel port
Data cache size: 16 Kbytes
Instruction cache size: 16 Kbytes
Secondary unified instruction/data cache size: 1 Mbyte
Main memory size: 64 Mbytes
Integral ISDN: Basic Rate Interface unit 0, revision 1.0
Integral Ethernet: ec0, version 1
Integral SCSI controller 0: Version WD33C93B, revision D
CDROM: unit 6 on SCSI controller 0
Disk drive / removable media: unit 5 on SCSI controller 0
Tape drive: unit 4 on SCSI controller 0: DAT
Disk drive: unit 3 on SCSI controller 0
Disk drive: unit 1 on SCSI controller 0
Graphics board: Indy 24-bit
Vino video: unit 0, revision 0, IndyCam connected

what I need to know. Is there a way to upgrade my
Secondary unified instruction/data cache size to 2 meg. like you have done in
your INDIGO 2's

Bob Haskin, Owner
CADDman
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