R4000 I-Cache

R4000 I-Cache

Post by Doug Kwan ~{9XUq5B » Sun, 07 Aug 1994 01:13:33



I have been writing a program involving run-time code generation on an
R4000 Indigo. I use the cacheflush system call but my program dies and
leaves a core if I use cacheflush( address, length, ICACHE ) whereas it
runs fine if either DCACHE | BCACHE is specified. Am I supposed to flush the
Instruction cache and only the Instruction cache alone? My program sorta
works like this.

        unsigned        foo[1024];      /* aligned to VM page boundary */      
        typedef (*func)();
        .
        .
        gencode( foo ); /* generate codes and store them in foo */
        cacheflush( foo, 4096, ICACHE );
        ((func)foo)();

Any info/answer/hint would be appreciated.

-Doug  

 
 
 

R4000 I-Cache

Post by Zalman Ste » Sun, 07 Aug 1994 20:25:02


Doug Kwan ~{9XUq5B~} writes

Quote:> I have been writing a program involving run-time code generation on an
> R4000 Indigo. I use the cacheflush system call but my program dies and
> leaves a core if I use cacheflush( address, length, ICACHE ) whereas it
> runs fine if either DCACHE | BCACHE is specified.

You must flush both caches. The data is written to the D cache as it is  
generated. You must flush this cache so that the data is stored through to  
memory as the I cache only reads from memory, not the D cache. (Actually, if  
you have a unified L2 cache, you can get away with only flushing the L1  
caches, but I doubt the OS gives you a way to say that.) You must flush the  
I cache so that there is no stale data at the addresses you wish to execute  
from.

There are a few performance optimizations that can be done if need be. Many  
of these depend on allocating a large chunk of memory and then flushing the  
entire I cache so that you know none of the addresses in the buffer are  
stale. You can then get by without I cache flushes until you run out of  
space in the buffer.
--

Adobe Systems, 1585 Charleston Rd., POB 7900, Mountain View, CA 94039-7900
It seems like once people grow up, they have no idea what's cool. - Calvin

 
 
 

R4000 I-Cache

Post by Zalman Ste » Tue, 09 Aug 1994 09:57:50


Doug Kwan ~{9XUq5B~} writes

Quote:> I have been writing a program involving run-time code generation on an
> R4000 Indigo. I use the cacheflush system call but my program dies and
> leaves a core if I use cacheflush( address, length, ICACHE ) whereas it
> runs fine if either DCACHE | BCACHE is specified.

You must flush both caches. The data is written to the D cache as it is  
generated. You must flush this cache so that the data is stored through to  
memory as the I cache only reads from memory, not the D cache. (Actually, if  
you have a unified L2 cache, you can get away with only flushing the L1  
caches, but I doubt the OS gives you a way to say that.) You must flush the  
I cache so that there is no stale data at the addresses you wish to execute  
from.

There are a few performance optimizations that can be done if need be. Many  
of these depend on allocating a large chunk of memory and then flushing the  
entire I cache so that you know none of the addresses in the buffer are  
stale. You can then get by without I cache flushes until you run out of  
space in the buffer.
--

Adobe Systems, 1585 Charleston Rd., POB 7900, Mountain View, CA 94039-7900
It seems like once people grow up, they have no idea what's cool. - Calvin

 
 
 

1. 'primary i-cache: !?!Syndrome'???

Hi SGI,

what does the following message I picked up from /usr/adm/SYSLOG
mean ?

Dec 11 13:19:25 2A:zonk unix:     ERROR MSG:  No ecc data error found in primary cacheline
Dec 11 13:19:25 2A:zonk unix:     primary i-cache: |?!Syndrome at addr 0xafee868 normal!
Dec 11 13:19:25 2A:zonk unix:     ERROR MSG:  No ecc data error found in primary cacheline
Dec 11 13:19:25 2A:zonk unix:     primary i-cache: |?!Syndrome at addr 0x83ee868 normal!

The machine is an Indy with R4600PC, running IRIX 5.2:

1 100 MHZ IP22 Processor
FPU: MIPS R4610 Floating Point Chip Revision: 0.0
CPU: MIPS R4600 Processor Chip Revision: 1.0
On-board serial ports: 2
On-board bi-directional parallel port
Data cache size: 16 Kbytes
Instruction cache size: 16 Kbytes
Main memory size: 64 Mbytes
etc..

Is there anything wrong with the hardware ?

Thanks,


------------------------------------------------------------------------
Andres Kruse      | NIKHEF - National Institute for Nuclear Physics and

------------------------------------------------------------------------

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