Size of Secondary Cacheline and Cost of Filling it

Size of Secondary Cacheline and Cost of Filling it

Post by Stig Larse » Tue, 23 Sep 1997 04:00:00



Is there a way of querying a SGI with R10K processor (specifically the
Power Challenge, Origin200, Octane and O2 architectures) for the
configured size of its secondary cache lines?

I have been looking at the list of typical cost (see 'perfex -t') of
each event that may be counted on the Performance Counters. On an Octane
it reports 396 cycles and on Origin200 only 76. Could someone please
briefly explain the reason for this? Or even better; is there an
accessible document that explains it?

Thank you in advance

Stig Larsen

 
 
 

Size of Secondary Cacheline and Cost of Filling it

Post by Dave Ols » Thu, 25 Sep 1997 04:00:00


| Is there a way of querying a SGI with R10K processor (specifically the
| Power Challenge, Origin200, Octane and O2 architectures) for the
| configured size of its secondary cache lines?

Nope.  None that I can remember.  The *PROM* hinv -t command on all
the O-series systems will show it, though.  It's 128 bytes for both
of those machines.  It's 32 bytes for r5k O2, and 64 bytes for r10k O2.

| I have been looking at the list of typical cost (see 'perfex -t') of
| each event that may be counted on the Performance Counters. On an Octane
| it reports 396 cycles and on Origin200 only 76. Could someone please
| briefly explain the reason for this? Or even better; is there an
| accessible document that explains it?

This doesn't sound right.  There have been a few bug fixes in the kernel
support for perfex, so make sure you have those, or the counter values
might not be right.  octane has very slightly lower memory latency
than origin, in almost all cases.
--

Dave Olson, Silicon Graphics


 
 
 

Size of Secondary Cacheline and Cost of Filling it

Post by Omar G. Stradell » Thu, 25 Sep 1997 04:00:00



> | I have been looking at the list of typical cost (see 'perfex -t') of
> | each event that may be counted on the Performance Counters. On an Octane
> | it reports 396 cycles and on Origin200 only 76. Could someone please
> | briefly explain the reason for this? Or even better; is there an
> | accessible document that explains it?

> This doesn't sound right.  There have been a few bug fixes in the kernel
> support for perfex, so make sure you have those, or the counter values
> might not be right.  octane has very slightly lower memory latency
> than origin, in almost all cases.
> --

It's a bug in the hardcoded table (it's showing ns instead of clocks).
The up-to-date values for IP30 are: 77.22 clks (typ), 41.83 clks (min)
and 81.87 clks (max).

Omar.
--
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Silicon Graphics, Inc.                          Computational Chemistry
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1. Secondary unified instruction/data cache size

I have the following INDY machine:

Iris Audio Processor: version A2 revision 4.1.0
1 150 MHZ IP22 Processor
FPU: MIPS R4010 Floating Point Chip Revision: 0.0
CPU: MIPS R4400 Processor Chip Revision: 5.0
On-board serial ports: 2
On-board bi-directional parallel port
Data cache size: 16 Kbytes
Instruction cache size: 16 Kbytes
Secondary unified instruction/data cache size: 1 Mbyte
Main memory size: 64 Mbytes
Integral ISDN: Basic Rate Interface unit 0, revision 1.0
Integral Ethernet: ec0, version 1
Integral SCSI controller 0: Version WD33C93B, revision D
CDROM: unit 6 on SCSI controller 0
Disk drive / removable media: unit 5 on SCSI controller 0
Tape drive: unit 4 on SCSI controller 0: DAT
Disk drive: unit 3 on SCSI controller 0
Disk drive: unit 1 on SCSI controller 0
Graphics board: Indy 24-bit
Vino video: unit 0, revision 0, IndyCam connected

what I need to know. Is there a way to upgrade my
Secondary unified instruction/data cache size to 2 meg. like you have done in
your INDIGO 2's

Bob Haskin, Owner
CADDman
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