Reseting the MCSR0 Register on a SPARC CPU 5V

Reseting the MCSR0 Register on a SPARC CPU 5V

Post by Andreas Golo » Fri, 18 Apr 1997 04:00:00



Hi there,
we have a problem to reset the bit 5 ( sysreset ) in the MCSR0 Register.
We tried to use memory mapping by mapping the address 0xffee3e0 ( base
address of the FGA-5000 ) with additional offest 0x1e0 of the mcsr0
regiger with the device /dev/kmem. But while trying to read at this
address an buserror occours. Does anybody know know what address we
should use instead to get to the FGA-5000 on the SPARC CPU 5V ?, or what
else could be the reason why this won't work.
We tried to access the LED's on this CPU with mapping of the address
0xffee2000 plus offest an it worked well with the same syntax. So what's
wrong ?

Thanks in advance

Andy

 
 
 

1. Problems mapping VME memory on Sparc 5V board

Help, please!

In our VME system, we are using a Sparc 5V board with 32M of memory, and
we are
trying to map the memory of a few other VME boards (16M/board) into the
kernel.  
If we have one or two of the VME boards (for a total of up to 32M of
memory to be
mapped), the system successfully completes the mapping.  However, when a
third
VME board is added (bringing the total memory to be mapped up to 48M),
the
system hangs right after mapping the memory on the first and second
boards.

Our first impression is that we are hitting to limit to the amount of
memory
that can be mapped on a VME system.  Does anybody know what that limit
is?  Has
anybody seen anything like this before?

Any suggestions will be greatly appreciated
MP
--
Miguel A. Pabon
Raytheon E-Systems
Falls Church, VA 22046

"The opinions expressed here are mine and not that of my employer."

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