Intel 21555 Non-transparent PCI-to-PCI bridge configuration

Intel 21555 Non-transparent PCI-to-PCI bridge configuration

Post by Chirayush Dhr » Thu, 27 Sep 2001 03:39:30


I am designing a PCI card with the Intel 21555 on it to be used with a
PC with multiple PCI slots, running Red Hat Linux, kernel 2.4, as the
host. I am not using a local processor on the secondary side of the

By default, at power on, the 21555 attempts to load default
configuration from a serial ROM. The 21555 user manual describes
different initialization options, which includes one without local
processor and with serial ROM preload, which is the one that I am
trying to implement. It states that it is possible to initialize the
21555 without a local processor and with a serial preload - the serial
preload should clear the primary-lock-out-bit, thus enabling the
primary side, access to the secondary interface of the 21555. (The
21555 evaluation board has a serial ROM and DIP switch selections to
do this).  With this set up, I am trying to sense and access the
secondary side of the 21555 by plugging the 21555 eval board into our
host PC. I encounter problems doing this: at boot up, the system
(Linux OS and its BIOS) scans the PCI bus, sniffing out devices and
configuring them. If it encounters a bridge (standard, transparent),
it sniffs beyond it and creates a device tree. Now, since the 21555 is
a non-transparent bridge, implementing a Header Type 0, the system
firmware cannot detect and configure devices on its secondary bus.

Can someone tell me how to configure and initialize the secondary side
of the 21555 ? Is it possible to do this from the device driver of the
card (that is loaded after boot up, I guess) or does it require
changes into the Kernel code, and a rebuild of the kernel ?

Thanks for the help, in advance !
-chirayush dhruv


1. Intel 21555 P2P bridge: configuration question

I am working with a client that is developing an intelligent PCI
adapter employing the Intel 21555 Non-transparent PCI bridge. They
have elected to not employ a serial ROM preload, and their local
processor is not ready for prime time, so I am trying to configure the
bridge BARs purely from the primary.

I am trying to implement the "indirect configuration" briefly
in section 6.3.4 of the July 2001 Intel guide (Intel 278321-002).

I am pursuing indirect configuration because host-side code - as well
as established tools such as 'pcitweak' - seem not to be able to write
to the BAR Setup registers (from the host/primary), even though the
Primary Access Lockout has been overridden. This was unexpected.

If you have advice, know of an example of this in code somewhere,
anything - I would be grateful.

The client's prototype has properly strapped pr_ad[3] down to override
the primary lockout. I ensure that the Downstream Transaction Enable
set, then attempt Type 1 transactions via the Downstream Transaction
Address and Data registers using I/O access (via BAR1). I am seeing no
valid responses in my efforts to probe the downstream/local bus. I am
experiementing with Type 0 and Type 1 on the Downstream, to no avail.

Thanks in advance for any leads you may have to share!

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