DRAM problem (kernel 1.1.94) - Please help!!!

DRAM problem (kernel 1.1.94) - Please help!!!

Post by Dr. Andreas Kard » Tue, 09 May 1995 04:00:00



Hi all,

I was running Linux on a 386DX40 with Symphony chipset, 4 MB
RAM, 2 IDE hard disks and one IDE CD-ROM drive. After upgrading
it to 16 MB RAM (4 SIMMs with 2 16MB and 1 4MB chips) a lot of
problems have appeared.

Under DOS it always runs normaly. The problems under Coherent I
could solve by changing the refresh mode from "normal" to
"decoupled refresh". Thats clear because the RAMs may require a
4K refresh cycle (12 address bits necessary for refresh of all
rows). My board probably provides only 2K refresh cycles. But
in the alternate refresh mode the DRAMs are using internal
counters, so that the refresh cycle doesn't matter.

This configuration also works normaly with an older Linux 1.0.8
kernel from a one year old Slackware CD. Because this kernel
doesn't support IDE CD-ROM drives I want to use a 1.1.94
kernel.

This kernel worked normaly on my box with 4 MB RAM. But with
16 MB shortly after boot or during boot I get a lot of error
messages (e.g. "no more processes in this run level", file
system errors, swaping errors and so on). I couldn't write them
down because they come very quickly. In the syslog and in the
other admin files isn't any helpful information.

I couldn't fix the problems with recompilations of the kernel
(under 1.0.8). I have tried it with and without the "limit to
lower 16 MB" option.

I think that these problems have something to do with the
timing of the RAM. Does the kernel (version 1.1.xx) change the
BIOS setup in some way or does it access the ICs of the chipset
directly?

Does anybody have an idea how to solve the problems?

Many thanks in advance

Andreas
--
Greetings from Wiesbaden, Germany

 
 
 

DRAM problem (kernel 1.1.94) - Please help!!!

Post by snea.. » Wed, 10 May 1995 04:00:00


Quote:>Under DOS it always runs normaly. The problems under Coherent I  
>could solve by changing the refresh mode from "normal" to  
>"decoupled refresh". Thats clear because the RAMs may require a  
>4K refresh cycle (12 address bits necessary for refresh of all  
>rows). My board probably provides only 2K refresh cycles. But  
>in the alternate refresh mode the DRAMs are using internal  
>counters, so that the refresh cycle doesn't matter.

i dont know if this even applies or not, but there is a utility called "dram" which  
lets you adjust your dram refresh rate on the fly. it's in the sunsite archives.

 
 
 

1. DRAM problem (kernel 1.1.94) - Please help!!!

Hi all,

I was running Linux on a 386DX40 with Symphony chipset, 4 MB
RAM, 2 IDE hard disks and one IDE CD-ROM drive. After upgrading
it to 16 MB RAM (4 SIMMs with 2 16MB and 1 4MB chips) a lot of
problems have appeared.

Under DOS it always runs normaly. The problems under Coherent I
could solve by changing the refresh mode from "normal" to
"decoupled refresh". Thats clear because the RAMs may require a
4K refresh cycle (12 address bits necessary for refresh of all
rows). My board probably provides only 2K refresh cycles. But
in the alternate refresh mode the DRAMs are using internal
counters, so that the refresh cycle doesn't matter.

This configuration also works normaly with an older Linux 1.0.8
kernel from a one year old Slackware CD. Because this kernel
doesn't support IDE CD-ROM drives I want to use a 1.1.94
kernel.

This kernel worked normaly on my box with 4 MB RAM. But with
16 MB shortly after boot or during boot I get a lot of error
messages (e.g. "no more processes in this run level", file
system errors, swaping errors and so on). I couldn't write them
down because they come very quickly. In the syslog and in the
other admin files isn't any helpful information.

I couldn't fix the problems with recompilations of the kernel
(under 1.0.8). I have tried it with and without the "limit to
lower 16 MB" option.

I think that these problems have something to do with the
timing of the RAM. Does the kernel (version 1.1.xx) change the
BIOS setup in some way or does it access the ICs of the chipset
directly?

Does anybody have an idea how to solve the problems?

Many thanks in advance

Andreas
--
Greetings from Wiesbaden, Germany

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