|> I am studying the posibility of incorporating the 68EC040(in companion mode) to a
|> 60360 design.
|> As I was looking through the 68360 users manual I noticed that by configuring the
|> for MC68040 companion mode (CONFIG pins = 011), the global chip select is automat
|> set to 32-bit size. The problem is that our current design is optimized for 8-bi
|> boot PROM. How can companion mode work in such a system, or will it?
You will either have to fake out the boot prom to look like a 32 bit
device, or boot from a 32 bit device. There is no dynamic bus-sizing
in 040 companion mode. I think Motorola makes a seperate chip to do this.
I saved a post a while back that talked about a way to hook up an 8-bit
PROM in this scenario. It is included below:
Article: 1337 of comp.sys.m68k
Subject: Re: Booting a 68000 with a single 8-bit EPROM
Date: 26 Jun 1994 16:35:37 GMT
First of all I think it's more trouble than it's worth IMHO. Reason being that
Quote:>Howdy! I am currently building a 68000 design and would like to boot off
>a single byte-wide EPROM instead of two byte-wide EPROMS. I have heard of
>of an implementation of this for the 68040. I'm sure it requires a custom
>PAL and a couple of latches. Any help would be greatly appreciated.
any alternative solution will require more wiring and more area than the
second EPROM. Writing a byte splitter is a 15 minute excercise and many modern
eprom programmer's software have the function built in.
However some suggestions:
1) Upgrade to a 68020 or 68030 or 683XX. All of these chips have DSACKX inputs
so that you can specify the size of the bus for each access.
2) Use a small microcontroller and a serial EEPROM. That way you can lose
the EPROM altogether and have the microcontroller program the RAM in
your system. Also it can provide you a reset circuit. Also since it's
EEPROM you can build the circuit so that it's downloadable from a serial
or parallel port and requires no erasure cycle.
3) The solution you suggested. Use a couple of 74HCT573 (or HCT373 if you like
odd wiring) and a state machine in a GAL to do the following:
1) Select the address with A0=0.
2) Latch the output byte to the D15-D8 latch.
3) Select the address with A0=1.
4) Latch the output byte to the D7-D0 latch.
5) Assert DTACK.
But 3) it makes it twice a slow (unless you use high speed EPROMS) and
requires quite a bit of extra ciruitry.
I'm planing on solution 2 in my next design. No EPROM just RAM and a
microcontroller (probably a PIC 16C54) and serial EEPROM solution.
Hope this helps,
Another random extraction from the mental bit stream of...
Byron A. Jeff - PhD student operating in parallel - And Using Linux!
Rodney Allen Boles
ibm: boles at ralvm29