What is propper sequence for clearing CISR Register bits

What is propper sequence for clearing CISR Register bits

Post by Thomas Doerfl » Wed, 06 Mar 1996 04:00:00




>The MC68360 QUICC manual gives an example of an SCC Interupt Handler.
>In Rev 1 of the manual, it is at the very end of chapter 7, in section
>7.15.6.2, page 7-381.  In this example, the SCC1 bit in the CISR is cleared
>*AFTER* the events for SCC1 are handled.  To me, this seems backwards.
>Can someone tell me the right way to do it, and explain to me why?

As long as you are talking about the SCCE event entries, you are
right, they should be cleared *BEFORE* they are processed, otherwise
for example new buffers that come up shortly after your buffer
processing loop might not be recognized as soon as possible (their
event bits would be cleared although the buffers were not processed).

The CISR has an other meaning: It simply indicates what interrupt
service functions are "In Service", and, this is its *MAIN* function,
it blocks any other interrupt sources of same or lower priority from
requesting interrupt. So the CISR is the key register to implement
nested interrupts for CP interrupt sources.

As long as a bit is set in the CISR, no lower priorized CPIC IRQ
source can request an interrupt. This means that you can establish the
following structure to your IRQ functions (here for SMC1):

1. examine and store the current IRQ mask value in the status register
of the CPU (I2-I0).

2. Lower the IRQ mask level in the CPU's status register by one (for
example from 4 to 3).
This will allow higher priorized IRQ sources in the CPIC (PC0 for
example) to "interrupt" the processing of the current interrupt
function (nested and priorized CPIC interrupts!). Note that the same
or a lower-priorized IRQ source (PC11 for ex.) in the CPIC cannot
interrupt the processing of the current IRQ function, since these
sources are blocked by the SMC1 bit set in CISR.

3. process your interrupt (this is complicated enough, smile...). This
includes clearing the SMC event register etc...

4. reestablish the original value of the IRQ mask in the SR of the CPU
(to 4 for example)

5. clear the SMC1 bit in the CISR. This will enable requests from
lower priority IRQ sources as well, but they are now blocked because
of the IRQ mask in the SR of the CPU

6. finally return from exeption (RTE).

Huuh, this is quite complicated, but compare it to the NOTE in chapter
7.15.5.4 in the MC68360 UM/AD Rev1.

If you have any more questions, please feel free to contact me again.

 Bye,
        Thomas.

Quote:>Thanks.

--------------------------------------------
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Thomas Doerfler           Elilandstrasse 12
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