Very Computer

I am using CodeWarrior 6.5 for embedded power pc ( MPC555 )

I'm trying to set the processor to use Non IEEE floating point mode by
setting the FPSCR.NI bit to 1. I am attempting to do this in the Debug
Initialization Script with the command.

# Use NON IEEE Floating Point Mode
writereg FPSCR 0x4;

However when debugging the application I find that this bit has not been set
in the FPSCR. In fact I don't seem to be able to set any bits in the FPSCR
from the debug initialization script.

I have not had problems with the the debug initialization scripts before.
All other registers I have attempted to configure have been handled with no
problems.

Is there a special way to configure the FPSCR from within CodeWarrior. I use
an almost identical command within the WindRiver SingleStep de* and I
get the result I require.

Brad Phelan
Senior Engineer
The Mathworks

http://www.veryComputer.com/

This should work on R6.5 of the tools just fine (setting the FPSCR
from the initialization file) using a stationery project for the Axiom
555 board.

Please note that the FPSCR is changed at the very bottom of the file I
am including below.

I am including a sample initialization file below for reference that
works just fine....the FPSCR setting has just been appended to the
normal init file that you would use for the Axiom board:

SAMPLE INIT FILE:
=========================================================
;----------------------------------------------------------------
; Standard Initialization Code for AXIOM CME-555 Evaluation Board
;----------------------------------------------------------------

writereg MSR 0x00003002 ; MSR
writespr 27 0x3002 ; SSR1

;Enable internal flash (CMF A at 0x0-0x3FFFF, CMF B at
0x40000-0x6FFFF)
writespr 638 0xfff00800 ; IMMR set FLEN bit in IMMR register
(overwrites RCW register, FLEN flag)

writespr 560 0x0000 ; BBCMCR
writemem.l 0x002fc384 0x55ccaa33 ; PLPRCRK: open key

;Problem on CME-555 board: SIUMCR set the IRQ0 (NMI) to a SPGOC0
writemem.l      0x002FC000      0x00000800

;(disable) watch dog / SYPCR=0xFF88
writemem.l      0x002FC004      0xFFFFFF88
;writemem.l     0x002FC004      0x0000FF88

;CS0:OR0 and BR0 move the external monitor chip mapping to 0x00400000
(64 kBytes at 0x400000-0x40FFFF)
writemem.l      0x002FC100      0x00400803      ;BR0: 16-bit port
writemem.l      0x002FC104      0xFFFF0020      ;OR0: 2 wait state,
asynchronous operation 40 Mhz clock, 70 ns

;CS1:OR1 and BR1 external SRAM at address 0x00C00000 (512 KBytes at
0xC00000-0xC7FFFF)
writemem.l      0x002FC108      0x00C00003      ;BR1: 32-bit port
writemem.l      0x002FC10C      0xFFF80002      ;OR1: 1 wait state,
asynchronous operation

;CS2:OR2 and BR2 external FLASH at address 0x00800000 (1 MByte at
0x800000-0x8FFFFF)
writemem.l      0x002FC110      0x00800003      ;BR2: 32-bit port
writemem.l      0x002FC114      0xFFF00022      ;OR2: 1 wait state,
cycle length, asynchronous operation

;set PLPRCR to have 40 MHz (required by GMD driver for flashing)
writemem.l      0x002FC284      0x00910000

writemem.l 0x002fc140 0x00000001 ; DMBR
writemem.l 0x002fc144 0x00000000 ; DMOR
writemem.w 0x00300000 0x0000 ; DPTMCR
writemem.w 0x00300004 0xffa0 ; RAMBAR
writemem.w 0x00305014 0x0000 ; PORTQS
writemem.w 0x00305016 0x0000 ; PQSPAR/DDRQS
writemem.w 0x00306100 0x0000 ; MPIOSMDR
writemem.w 0x00306102 0x0000 ; MPIOSMDDR
writemem.w 0x00306800 0x0000 ; MIOS1TPCR
writemem.l 0x00380000 0x00000000 ; SRAMMCR
writemem.l 0x002fc024 0x00000000 ; SGPIODT1
writemem.l 0x002fc028 0x00000000 ; SGPIODT2
writemem.l 0x002fc02c 0x00000000 ; SGPIOCR
writemem.l 0x002fc030 0x00000000 ; EMCR
writemem.l 0x00307f80 0x00000000 ; UMCR

#--------------------------------------------------------------------
# The de* sets the DER register based on the EPPC Exceptions
# preference panel after running this initialization file, this
# this value will be overwritten.  We only put it in here because
# the flash programmer uses this file also.
#--------------------------------------------------------------------
writereg        DER             0x73e67c0f
writereg        FSPCR   0x4     ; set to Non-IEEE mode
=====================================================================

Regards,
John

On Thu, 10 Apr 2003 10:00:29 +0100, "Brad Phelan"