PC DMA Question - compressed DMA cycles?

PC DMA Question - compressed DMA cycles?

Post by Joseph J. Kubic » Thu, 10 Jun 1993 03:37:07

There's a bit in the 8237 DMA controller command register that
selects a "Special Compressed DMA Bus Cycle" (bit 3).  However,
my book (Interfacing to the IBM PC...) says not to use it because
it will cause the DMA to violate some specified limits for access
time.  It seems like it would probably work anyway, given most
cards are capable of pretty fast I/O access these days.  Has anyone
ever tried this?

Jay Kubicky


1. Help! Question about PC DMA controller programming

Would anybody help me with DMA controller programming?

I wrote a driver for my ADC/DAC card using DMA in IBM PC/AT for DOS.
There were a code in it:

  unsigned p1 , p2 ;
  asm {
    mov al,59h //DMA channel1 mode setting, single byte input, autoinitialization
    out 8,al }
    p1 = DMApos() ;
  while( p1 < p2 ) ;



  unsigned DMApos() {   //getting current address of channel 1
    asm {
      out  0ch,al       //clear low byte flip/flop
      in   al,2         //read channel 1 current address low byte
      mov  ah,al
      in   al,2         //read channel 1 current address high byte
      xchg al,ah
      sti }
    return _AX ; }

When I remove printf or redirect it to nul: some data incoming from
ADC are lost :-(. WHY?!

The DMA controller was programed to single byte input,
autoinitialization ( out 8,59h ), period of DRQ's was about
10 - 100 microseconds.

So, the questions:
  1. What do 8237 do with DRQ's between port 2 readings?
     Can it loss DRQ's in this time?
  2. Can it loss DRQ's while other DRQ treatment or memory refresh?
     In my computer DRQ0 seems to be unused.
  3. Can it loss DRQ's during autoinitialization?

                                        Best regards,
                                        Waldemar G. Saitseff
Speech Technology Center
Phone: (812)532-5903

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