Can you PLEASE see if there is CPM parameter ram conflict here?

Can you PLEASE see if there is CPM parameter ram conflict here?

Post by Subodh Nijsu » Mon, 18 Jun 2001 22:12:06



Hello,

I have a 860P design where I am using SMC1 and SMC2 for UART and
SCC1 and SCC2 for ethernet.
Also on this board I will be using I2C only ONCE to read the SDRAM
and SEEPROM information after which I have no use of I2C.

As far as I can tell there is no CPM parameter RAM conflict, does anybody
know if there are possible problems using this type of configuration?

/SUbodh Nijsure

 
 
 

Can you PLEASE see if there is CPM parameter ram conflict here?

Post by Thomas Doerfl » Tue, 19 Jun 2001 04:12:26


Hi,



Quote:>Hello,

>I have a 860P design where I am using SMC1 and SMC2 for UART and
>SCC1 and SCC2 for ethernet.
>Also on this board I will be using I2C only ONCE to read the SDRAM
>and SEEPROM information after which I have no use of I2C.

Well, you can't use I2C and SCC1/Ethernet at the same time, but if you
stop I2C befoer you start up SCC1 as Ethernet, your parameter RAM
layout is ok.

By the way: There is a microcode patch on Motorola's web server to
even use I2C and SCC1/Ethernet at the same time, it allows you to
relocate the I2C (and SPI) parameters to an unused area anywhere in
DPRAM.

Bye,
        Thomas Doerfler.

Quote:

>As far as I can tell there is no CPM parameter RAM conflict, does anybody
>know if there are possible problems using this type of configuration?

>/SUbodh Nijsure

--------------------------------------------
IMD Ingenieurbuero fuer Microcomputertechnik
Thomas Doerfler           Herbststrasse 8
D-82178 Puchheim          Germany


 
 
 

Can you PLEASE see if there is CPM parameter ram conflict here?

Post by Tom Evan » Tue, 19 Jun 2001 16:46:34




Quote:> I have a 860P design where I am using SMC1 and SMC2 for UART and
> SCC1 and SCC2 for ethernet.
> Also on this board I will be using I2C only ONCE to read the SDRAM
> and SEEPROM information after which I have no use of I2C.

Then it might be easier to wave the PB26 and PB27 pins
around yourself using a software emulation of I2C.

If you don't, watch out - they may be a "two byte delay" required
after transmits - maybe this is the 823 though.

Search for "I2C" in this group on groups.google.com. You'll find
at least 51 entries...

Check the Errata. Even the 860 Rev C.1 has 8 I2C errata items!

Tom Evans
InitialSurnameAt
tennyson.com.au

 
 
 

Can you PLEASE see if there is CPM parameter ram conflict here?

Post by Wolfgang Den » Thu, 21 Jun 2001 07:58:13





>> Also on this board I will be using I2C only ONCE to read the SDRAM
>> and SEEPROM information after which I have no use of I2C.
>Then it might be easier to wave the PB26 and PB27 pins
>around yourself using a software emulation of I2C.

...which should be especially easy, since  Subodh  is  using  PPCBoot
which already includes a soft_i2c driver...

Wolfgang Denk

--
Software Engineering:  Embedded and Realtime Systems,  Embedded Linux
Phone: (+49)-8142-4596-87  Fax: (+49)-8142-4596-88   Web: www.denx.de
Living on Earth may be expensive, but it includes an annual free trip
around the Sun.

 
 
 

Can you PLEASE see if there is CPM parameter ram conflict here?

Post by Richard Hendrick » Sat, 30 Jun 2001 12:48:39


Well, the 2 byte delay is because of the FIFO and transmit holding
register, but I digress.  Just be aware that multimaster I2C on the
8xx family is so buggy as to be practically useless.




> > I have a 860P design where I am using SMC1 and SMC2 for UART and
> > SCC1 and SCC2 for ethernet.
> > Also on this board I will be using I2C only ONCE to read the SDRAM
> > and SEEPROM information after which I have no use of I2C.

> Then it might be easier to wave the PB26 and PB27 pins
> around yourself using a software emulation of I2C.

> If you don't, watch out - they may be a "two byte delay" required
> after transmits - maybe this is the 823 though.

> Search for "I2C" in this group on groups.google.com. You'll find
> at least 51 entries...

> Check the Errata. Even the 860 Rev C.1 has 8 I2C errata items!

> Tom Evans
> InitialSurnameAt
> tennyson.com.au

--
"Never apply a Star Trek solution to a Babylon 5 problem." --FermiLab
 
 
 

1. MPC860 parameter ram conflicts.

Hi everyone.

I am going to develop my own custom board with PowerPC860 using vxWorks.
And I have a problem with the parameter ram conflict of between
SCC3(ethernet) and SMC1(UART).

I have already microcode for patch. And I applied microcode patch to my BSP.
But, It's not to work.
I think that the matter is to set of relocatable register(may be...).

Any comments would be appreciated...
Thanks.


2. Online forums for FM?

3. failure to power up, keyboard not seen, drive A not seen, monitor not seen

4. X11 forwarding with ssh2

5. SCSI card sees scanner 8 times (not an ID conflict!)

6. -- HE330 vs Sony SJ20: screen durability, display quirks

7. has anyone else seen this or am I just high?

8. ANNOUNCE: New Article on Language Selection

9. AM I THE ONLY 1 THAT SEES THIS?

10. problem with map_set (what AM i seeing?)

11. LL(1) conflict resolution for parameters

12. UMAX 610S/RAM Doubler Conflict

13. PC install of 3.3 only sees 16 MG of RAM