Internal / External Multiplexing; Sync Instruction

Internal / External Multiplexing; Sync Instruction

Post by Tim Ame » Thu, 06 May 1999 04:00:00



Good Afternoon,

I've been working on an MPC860 project. Up until recently, I've been
using internal
multiplexing on the dram. But it turns out that since we have another
PCI bus
master in the circuit, I have to use external multiplexing.

I have cleared the SAM bit in the appropriate OR register. The code runs
fine with
external multiplexing.....until the instruction cache is unlocked.

The code "blows-up" on the   sync   instruction in the that is noted in
the attached
code fragment.

Any ideas?

Tim

#************************************************************************

#   Function: CacheInit
*
#   PURPOSE: LowLevel Cache Initialization Code (from init.s)
*
#************************************************************************

        .text
        .align   4

#************************************************************************

# Cache Initialization
*
#
*
# Function: CacheInit
*
#       If the Data cache is enabled, flush then
*
#       disable it so we can finish the rest of initialization
*
# Input Registers:
*
#       R8 contains the content of DC_CST before entering              *

# Output Registers:
*
#       R3, R4, R5 and R6 will be destroyed
*
#************************************************************************

        .text
        .align   4

        .globl   CacheInit
CacheInit:

#------------------------------------------------------------------------

# If Instruction cache was enabled, disable and invalidate all
#------------------------------------------------------------------------

ICacheInit:
    mfspr   r3,IC_CST            # read I-cache CSR
    andis.  r3,r3,CacheEnableBit
    beq     ICacheUnlock         # no, Icache was disabled

    lis     r3,CacheDisableCmd
    mtspr   IC_CST,r3            # disable Icache
    isync

ICacheUnlock:
    lis     r3,CacheUnlockAllCmd
    mtspr   IC_CST,r3            # Unlock Icache
    isync

ICacheInv:
    lis r3,CacheInvAllCmd
    mtspr   IC_CST,r3            # Invalidate Icache
    isync

#------------------------------------------------------------------------

# Turn on the instruction cache
#------------------------------------------------------------------------

ICacheEnable:
    lis     r3,CacheEnableCmd
    mtspr   IC_CST,r3            # Enable Icache
    isync

#------------------------------------------------------------------------

# Initialize the data cache.
#------------------------------------------------------------------------

DCacheInit:
DCacheUnlock:

    lis     r3,CacheUnlockAllCmd

    sync                               #*?*?*?*?*?*?*?*? CODE BLOWS UP
HERE

    mtspr   DC_CST,r3            # Unlock Dcache

    andis.  r8,r8,CacheEnableBit    # Was DCache enabled ?
    beq     DCacheInv            # no, Dcache was disabled

DCacheFlushAll:
    li      r3,0                 # Read 1 word per cache line
    li      r6,0                 # Read 1 word per cache line
#                                # for 800 lines
    li      r4,256               # 2 ways, 128 sets per way
DCacheFlushLoop:
    addic.  r4,r4,-1             # decrementer, set cc bit
    lwz     r5,0(r3)             # access memory
    dcbf    r6,r3                # flush the line
    addi    r3,r3,16             # next line
    bgt     DCacheFlushLoop

DCacheDisable:
    lis     r3,CacheDisableCmd
    sync
    mtspr   DC_CST,r3           # disable Dcache

DCacheInv:
    lis     r3,CacheInvAllCmd
    sync
    mtspr   DC_CST,r3           # Invalidate Dcache

#------------------------------------------------------------------------

# Turn on the data cache
#------------------------------------------------------------------------

DCacheEnable:
#   lis     r3,CacheEnableCmd
#   sync
#   mtspr   DC_CST,r3           # Enable Icache
#

 blr       # Return

 
 
 

Internal / External Multiplexing; Sync Instruction

Post by Richard Hendrick » Tue, 11 May 1999 04:00:00


Check your UPM timings, and make sure the SAM bit as well as the NA bit
is being appropriately set.  My guess would be that your burst read
timing is not right, and after enabling the caches, the core begins
burst-reading to fill the cache and croaks.

> Good Afternoon,

> I've been working on an MPC860 project. Up until recently, I've been
> using internal
> multiplexing on the dram. But it turns out that since we have another
> PCI bus
> master in the circuit, I have to use external multiplexing.

> I have cleared the SAM bit in the appropriate OR register. The code runs
> fine with
> external multiplexing.....until the instruction cache is unlocked.

> The code "blows-up" on the   sync   instruction in the that is noted in
> the attached
> code fragment.

> Any ideas?

> Tim

> #************************************************************************

> #   Function: CacheInit
> *
> #   PURPOSE: LowLevel Cache Initialization Code (from init.s)
> *
> #************************************************************************

>         .text
>         .align   4

> #************************************************************************

> # Cache Initialization
> *
> #
> *
> # Function: CacheInit
> *
> #       If the Data cache is enabled, flush then
> *
> #       disable it so we can finish the rest of initialization
> *
> # Input Registers:
> *
> #       R8 contains the content of DC_CST before entering              *

> # Output Registers:
> *
> #       R3, R4, R5 and R6 will be destroyed
> *
> #************************************************************************

>         .text
>         .align   4

>         .globl   CacheInit
> CacheInit:

> #------------------------------------------------------------------------

> # If Instruction cache was enabled, disable and invalidate all
> #------------------------------------------------------------------------

> ICacheInit:
>     mfspr   r3,IC_CST            # read I-cache CSR
>     andis.  r3,r3,CacheEnableBit
>     beq     ICacheUnlock         # no, Icache was disabled

>     lis     r3,CacheDisableCmd
>     mtspr   IC_CST,r3            # disable Icache
>     isync

> ICacheUnlock:
>     lis     r3,CacheUnlockAllCmd
>     mtspr   IC_CST,r3            # Unlock Icache
>     isync

> ICacheInv:
>     lis r3,CacheInvAllCmd
>     mtspr   IC_CST,r3            # Invalidate Icache
>     isync

> #------------------------------------------------------------------------

> # Turn on the instruction cache
> #------------------------------------------------------------------------

> ICacheEnable:
>     lis     r3,CacheEnableCmd
>     mtspr   IC_CST,r3            # Enable Icache
>     isync

> #------------------------------------------------------------------------

> # Initialize the data cache.
> #------------------------------------------------------------------------

> DCacheInit:
> DCacheUnlock:

>     lis     r3,CacheUnlockAllCmd

>     sync                               #*?*?*?*?*?*?*?*? CODE BLOWS UP
> HERE

>     mtspr   DC_CST,r3            # Unlock Dcache

>     andis.  r8,r8,CacheEnableBit    # Was DCache enabled ?
>     beq     DCacheInv            # no, Dcache was disabled

> DCacheFlushAll:
>     li      r3,0                 # Read 1 word per cache line
>     li      r6,0                 # Read 1 word per cache line
> #                                # for 800 lines
>     li      r4,256               # 2 ways, 128 sets per way
> DCacheFlushLoop:
>     addic.  r4,r4,-1             # decrementer, set cc bit
>     lwz     r5,0(r3)             # access memory
>     dcbf    r6,r3                # flush the line
>     addi    r3,r3,16             # next line
>     bgt     DCacheFlushLoop

> DCacheDisable:
>     lis     r3,CacheDisableCmd
>     sync
>     mtspr   DC_CST,r3           # disable Dcache

> DCacheInv:
>     lis     r3,CacheInvAllCmd
>     sync
>     mtspr   DC_CST,r3           # Invalidate Dcache

> #------------------------------------------------------------------------

> # Turn on the data cache
> #------------------------------------------------------------------------

> DCacheEnable:
> #   lis     r3,CacheEnableCmd
> #   sync
> #   mtspr   DC_CST,r3           # Enable Icache
> #

>  blr       # Return


 
 
 

Internal / External Multiplexing; Sync Instruction

Post by Thomas Riesenber » Wed, 12 May 1999 04:00:00


I have a scenario for this:

Until you enabled the caches there are no bursts on the internal
bus of the chip. When you cleared the SAM bit you disabled the
internal address multiplex only for the first UPM cycle.
For the subsequent cycles you have to clear also the AMX bits
in the UPM RAM word, and my guess is that you did not.

(If I am wrong please stop reading, I apologize!...)

So, when the cache was enabled, it will try to fetch 4 words
from the memory (after the isync execution).
From the memory controller's point-of-view the first cycle
will be OK (SAM bit cleared) and the right data will be fetched,
but the other cycles not.

Thomas


> Good Afternoon,

> I've been working on an MPC860 project. Up until recently, I've been
> using internal
> multiplexing on the dram. But it turns out that since we have another
> PCI bus
> master in the circuit, I have to use external multiplexing.

> I have cleared the SAM bit in the appropriate OR register. The code runs
> fine with
> external multiplexing.....until the instruction cache is unlocked.

> The code "blows-up" on the   sync   instruction in the that is noted in
> the attached
> code fragment.

> Any ideas?

> Tim

> #************************************************************************

> #   Function: CacheInit
> *
> #   PURPOSE: LowLevel Cache Initialization Code (from init.s)
> *
> #************************************************************************

>         .text
>         .align   4

> #************************************************************************

> # Cache Initialization
> *
> #
> *
> # Function: CacheInit
> *
> #       If the Data cache is enabled, flush then
> *
> #       disable it so we can finish the rest of initialization
> *
> # Input Registers:
> *
> #       R8 contains the content of DC_CST before entering              *

> # Output Registers:
> *
> #       R3, R4, R5 and R6 will be destroyed
> *
> #************************************************************************

>         .text
>         .align   4

>         .globl   CacheInit
> CacheInit:

> #------------------------------------------------------------------------

> # If Instruction cache was enabled, disable and invalidate all
> #------------------------------------------------------------------------

> ICacheInit:
>     mfspr   r3,IC_CST            # read I-cache CSR
>     andis.  r3,r3,CacheEnableBit
>     beq     ICacheUnlock         # no, Icache was disabled

>     lis     r3,CacheDisableCmd
>     mtspr   IC_CST,r3            # disable Icache
>     isync

> ICacheUnlock:
>     lis     r3,CacheUnlockAllCmd
>     mtspr   IC_CST,r3            # Unlock Icache
>     isync

> ICacheInv:
>     lis r3,CacheInvAllCmd
>     mtspr   IC_CST,r3            # Invalidate Icache
>     isync

> #------------------------------------------------------------------------

> # Turn on the instruction cache
> #------------------------------------------------------------------------

> ICacheEnable:
>     lis     r3,CacheEnableCmd
>     mtspr   IC_CST,r3            # Enable Icache
>     isync

> #------------------------------------------------------------------------

> # Initialize the data cache.
> #------------------------------------------------------------------------

> DCacheInit:
> DCacheUnlock:

>     lis     r3,CacheUnlockAllCmd

>     sync                               #*?*?*?*?*?*?*?*? CODE BLOWS UP
> HERE

>     mtspr   DC_CST,r3            # Unlock Dcache

>     andis.  r8,r8,CacheEnableBit    # Was DCache enabled ?
>     beq     DCacheInv            # no, Dcache was disabled

> DCacheFlushAll:
>     li      r3,0                 # Read 1 word per cache line
>     li      r6,0                 # Read 1 word per cache line
> #                                # for 800 lines
>     li      r4,256               # 2 ways, 128 sets per way
> DCacheFlushLoop:
>     addic.  r4,r4,-1             # decrementer, set cc bit
>     lwz     r5,0(r3)             # access memory
>     dcbf    r6,r3                # flush the line
>     addi    r3,r3,16             # next line
>     bgt     DCacheFlushLoop

> DCacheDisable:
>     lis     r3,CacheDisableCmd
>     sync
>     mtspr   DC_CST,r3           # disable Dcache

> DCacheInv:
>     lis     r3,CacheInvAllCmd
>     sync
>     mtspr   DC_CST,r3           # Invalidate Dcache

> #------------------------------------------------------------------------

> # Turn on the data cache
> #------------------------------------------------------------------------

> DCacheEnable:
> #   lis     r3,CacheEnableCmd
> #   sync
> #   mtspr   DC_CST,r3           # Enable Icache
> #

>  blr       # Return

--
 
 
 

1. Internal Vs External Modems & External modem power supplies

[ post.modems 1K ]

        External Or Internal modem ?

        Hi, I'm planning to buy a modem for my PC.

        Any expert advise on whether I should go for an external
        one or internal ?

        As I see, comparison goes as follows, (If anybody has more points
        pl. let me know).

        Internal modem :-

        Advantages :-
                Cheaper than external one.
                COM port is free.
                Faster transfer from PC to modem on ISA bus.
                Less clutter because modem does not require any space.
                .......

        Disadvantage :  

                Can only be used for the PC in which the card is installed.
                Occupies one ISA slot.

        ==============================================================

        External modem :

        Advantage :

                Can be used with any PC and even a standard RS232 terminal
                for dial up access.
                One ISA slot free.

        Disadvantage :

                Expensive compared to internal.
                COM port not free.

        Performance wise is there any difference between Internal
        and external modems ? Does anybody have figures to
        compare ? I though internal modem could be faster because
        data transfer between PC and modem is much faster (ISA bus
        transfer) compared to a serial transfer on COM port for
        an external modem.

        I have one question about usability of "External" modems on
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        on both power supplies ?

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