>eZ80: easy and simply 4 times faster?
>I've looked at the documentation of Zilogs new CPU, the eZ80 and think
>it is interesting. Even without changing the clock speed, it should be
>4 times faster than a standard Z80, which would mean a virtual 14,3
>MHz on a standard MSX and even 28,6MHz on a 7MHz machine. The CPU
>could run at higher clock speeds (up to 80MHz) but that would require
>major changes in the rest of the MSX-hardware.
>So, does anybody know if it would be possible to just pull out the old
>Z80A (or in some cases the Z80H) and replace it with the eZ80 (on a
>little printed circuit board to make it fit in a DIL-socket) ??? I'm
>not all that familiar with hardware and the Zilog site doesn't clarify
>if you can do that.
>Of course, in this case you wouldn't use the advanced posibilities of
>the eZ80, like directly addressing 64MB of RAM and using the internal
>TCP/IP stack which makes it easy to connect to the Internet. But at
>least it would be simple and 100% compatible.
>Any ideas, someone?
Zilog may not want to commit themselves at this
early stage. The current Processor Description
document is too incomplete to offer conclusions.
Up to page 16 of the eZ80 Operational Description,
the answer seems to be "Yes". But, at the bottom of
page 16, there is the following note:
"The Z80 and Z80180 instruction sets include an
RETI instruction that is used for servicing Z80
peripherals. Because the eZ80 does not include
these peripherals, nor does it allow them to be
connected externally, there is no reason to ever
conclude an eZ80 ISR with an RETI."
This is especially confusing, because earlier pages
discuss the IEI-IEO daisy-chain feature which is unique
to Z80 peripherals.
If the eZ80 runs 4 times faster than a Z80 at the same
clock frequency, there's a potential for problems with
memory i/o in an existing Z80 circuit -- particularly
with slower ROMs. And. timing loops may cause problems
with some i/o devices, such as floppy drives.
I think a bigger potential hassle with the eZ80 is the
mixed 16/24-bit architecture. Typical code that works in
Native Z80 mode will crash in ADL mode, and vice versa.
The eZ80 creates a new native data type: the 24-bit
integer, meaning that special compilers will need to be
written for it (the compiler makers will be delighted,
for the new business). How does the 24-bit integer work
within Zilog's little-endian world, where bytes/words
are stored in reverse order? For example, the following
two data lines are equivalent in a 16-bit little-endian
dw 1234H ; int
db 34H, 12H ; char, char
With long integers, these three lines are equivalent...
dd 12345678H ; longint
dw 5678H, 1234H ; int, int
db 78H, 56H, 34H, 12H ; char, char, ...
Is this the 24-bit integer/register scenario?...
dd 123456789ABCH ; longint
dw 789ABCH, 123456H ; int, int
db 0BCH, 9AH, 78H, 56H, 34H, 12H ; char, char, ...
The eZ80 programming model is also awkward: The
"Virtual Z80" mode is said to offer multiple Z80
tasks their own partitions -- but "interrupts and
trap locations are never mapped." This means that
*all* tasks must share common interrupt service
routines, located in the first 64k of memory.
September 24, 1999, Toronto.